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69 lines
2.6 KiB
C
69 lines
2.6 KiB
C
/* $NetBSD: bebox.h,v 1.2 2012/10/20 12:37:49 kiyohara Exp $ */
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/*
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* Copyright (c) 2011 KIYOHARA Takashi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _BEBOX_H
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#define _BEBOX_H
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/*
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* BeBox mainboard's Register
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*/
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#define BEBOX_REG 0x7ffff000
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#define BEBOX_SET_MASK 0x80000000
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#define BEBOX_CLEAR_MASK 0x00000000
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#define READ_BEBOX_REG(reg) *(volatile uint32_t *)(BEBOX_REG + (reg))
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#define SET_BEBOX_REG(reg, v) \
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*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_SET_MASK)
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#define CLEAR_BEBOX_REG(reg, v) \
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*(volatile uint32_t *)(BEBOX_REG + (reg)) = ((v) | BEBOX_CLEAR_MASK)
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#define CPU0_INT_MASK 0x0f0 /* Interrupt Mask for CPU0 */
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#define CPU1_INT_MASK 0x1f0 /* Interrupt Mask for CPU1 */
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#define INT_SOURCE 0x2f0 /* Interrupt Source */
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#define CPU_CONTROL 0x3f0 /* Inter-CPU Interrupt */
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#define CPU_RESET 0x4f0 /* Reset Control */
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#define INTR_VECTOR_REG 0xff0
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#define BEBOX_INTR_MASK 0x0ffffffc
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/* Control */
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#define CPU0_SMI (1 << 30) /* SMI to CPU0 */
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#define CPU1_SMI (1 << 29) /* SMI to CPU1 */
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#define CPU1_INT (1 << 28) /* Interrupt to CPU1 (rev.1 only) */
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#define CPU0_TLBISYNC (1 << 27) /* tlbsync to CPU0 */
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#define CPU1_TLBISYNC (1 << 26) /* tlbsync to CPU1 */
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#define WHO_AM_I (1 << 25)
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#define TLBISYNC_FROM(n) (1 << (CPU1_TLBISYNC + (n)))
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/* Reset */
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#define CPU1_SRESET (1 << 30) /* Software Reset to CPU1 */
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#define CPU1_HRESET (1 << 29) /* Hardware Reset to CPU1 */
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#endif /* _BEBOX_H */
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