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162 lines
4.6 KiB
ArmAsm
162 lines
4.6 KiB
ArmAsm
/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Fleischer <paul@xpg.dk>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#define _LOCORE
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#define _KERNEL
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#include <machine/asm.h>
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#include <arm/armreg.h>
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#include <arm/arm32/pte.h>
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#include <arm/arm32/pmap.h> /* for PMAP_DOMAIN_KERNEL */
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#include <arm/s3c2xx0/s3c2440reg.h> /* for S3C2440_SDRAM_START */
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#ifndef SDRAM_START
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#define SDRAM_START S3C2440_SDRAM_START
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#endif
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/* LED1/2/3/4 are manipulated by GPIO B5/6/7/8. */
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#define LED1 (1<<5)
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#define LED2 (1<<6)
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#define LED3 (1<<7)
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#define LED4 (1<<8)
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.text
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.global _start
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_start:
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/* Get arguments from boot-loader (stored in r0 and r1) */
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adr r2, Largs
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stmia r2, {r0, r1}
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/* Disable interrupt */
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mrs r0, cpsr
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orr r0, r0, #I32_bit
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msr cpsr, r0
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/* Turn off all LEDS except LED2 */
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mov r1, #S3C2440_GPIO_BASE
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add r1, r1, #0x14
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ldr r3, [r1]
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orr r3, r3, #LED1 /* LEDS are active-low, so we set their bit to turn them off */
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bic r3, r3, #LED2
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orr r3, r3, #LED3
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orr r3, r3, #LED4
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str r3, [r1]
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/* Setup BANK6/7 memory map */
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mov r1, #S3C2440_MEMCTL_BASE
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ldr r2, [r1, #MEMCTL_BANKSIZE]
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bic r2, r2, #0x7 /* Clear the three lowest bits (BK67MAP) */
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add r2, r2, #0x1 /* Set BK67MAP to b001 = 64MB/64MB */
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str r2, [r1, #MEMCTL_BANKSIZE]
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/* Disable MMU for a while */
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mrc p15, 0, r2, c1, c0, 0
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bic r2, r2, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r2, c1, c0, 0
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nop
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nop
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nop
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ldr r0, LpageTable /* pagetable */
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adr r4, mmu_init_table
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b 2f
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1:
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str r3, [r0, r2]
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add r2, r2, #4
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add r3, r3, #(L1_S_SIZE)
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adds r1, r1, #-1
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bhi 1b
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2:
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ldmia r4!, {r1,r2,r3} /* # of sections, PA|attr, VA */
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cmp r1, #0
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bne 1b
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mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
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mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
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/* Set the Domain Access register. Very important! */
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mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
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mcr p15, 0, r0, c3, c0, 0
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/* Enable MMU */
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #CPU_CONTROL_MMU_ENABLE
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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/* Prepare stack */
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adr r1, Lcrtsetup
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ldmia r1, {r1, r2, sp}
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sub r2, r2, r1 /* get zero init data */
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mov r3, #0
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.L1:
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str r3, [r1], #0x0004 /* zero the bss */
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subs r2, r2, #4
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bgt .L1
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adr r2, Largs
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ldmia r2, {r0, r1}
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/* Jump to kernel code in TRUE VA */
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ldr pc, Lstart
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Lstart:
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.word main
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#define MMU_INIT(va,pa,n_sec,attr) \
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.word n_sec ; \
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.word 4*((va)>>L1_S_SHIFT) ; \
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.word (pa)|(attr) ;
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mmu_init_table:
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/* fill all table VA==PA */
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MMU_INIT(0x00000000, 0x00000000, 1<<(32-L1_S_SHIFT), L1_TYPE_S|L1_S_AP(AP_KRW))
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/* map SDRAM VA==PA, WT cacheable */
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MMU_INIT(SDRAM_START, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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/* map VA 0xc0000000..0xc3ffffff to PA 0x30000000..0x33ffffff */
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MMU_INIT(0xc0000000, SDRAM_START, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
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.word 0 /* end of table */
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LpageTable:
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.word 0x30000000
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Lcrtsetup:
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.word _edata /* Start of BSS */
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.word _end /* End of BSS */
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.word 0x30A00000 /* Place stack-bottom at load-point of libsa bootloader */
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Largs:
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.space 8 /* to save r0/r1 registers */
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