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69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/* $NetBSD: mach_intr.c,v 1.2 2015/06/01 22:55:12 matt Exp $ */
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/*-
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* Copyright (c) 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Platform-specific interrupt support for the Alchemy parts.
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*
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* These boards just use the interrupt controller built into the
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* Alchemy processors, so we just provide evbmips-compliant wrapper
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* routines.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mach_intr.c,v 1.2 2015/06/01 22:55:12 matt Exp $");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/lwp.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/systm.h>
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#include <mips/locore.h>
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#include <mips/cavium/octeonvar.h>
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void
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evbmips_intr_init(void)
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{
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octeon_intr_init(curcpu());
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}
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void
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evbmips_iointr(int ipl, vaddr_t pc, uint32_t ipending)
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{
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octeon_iointr(ipl, pc, ipending);
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}
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