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83 lines
3.9 KiB
C
83 lines
3.9 KiB
C
/* $NetBSD: cadmusreg.h,v 1.2 2011/01/18 01:10:25 matt Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
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* Agency and which was developed by Matt Thomas of 3am Software Foundry.
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*
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* This material is based upon work supported by the Defense Advanced Research
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* Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
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* Contract No. N66001-09-C-2073.
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* Approved for Public Release, Distribution Unlimited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MPC85XX_CADMUSREG_H_
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#define _MPC85XX_CADMUSREG_H_
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#define CM_BASE 0xF8004000
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#define CM_VER 0x00 /* System version register */
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#define CM_VER_ID __BITS(4,7)
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#define CM_VER_ID_GET(n) __SHIFTOUT((n), CM_VER_ID)
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#define CM_VER_REV __BITS(0,3)
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#define CM_VER_REV_GET(n) __SHIFTOUT((n), CM_VER_ID)
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#define CM_CSR 0x01 /* General control/status register */
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#define CM_CSR_USER __BITS(6,7)
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#define CM_CSR_USER_GET(n) __SHIFTOUT((n), CM_CSR_USER)
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#define CM_CSR_EPHY __BITS(1,3)
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#define CM_CSR_EPHY_GET(n) __SHIFTOUT((n), CM_CSR_EPHY)
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#define CM_CSR_LED __BIT(0)
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#define CM_RST 0x02 /* Reset control register */
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#define CM_RST_XRSTEN __BIT(7) /* Enable the NVRAM watchdog timr to function as a general reset input */
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#define CM_RST_PHYRST __BIT(6) /* Reset the Ethernet PHY */
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#define CM_RST_ATM1RST __BIT(5) /* Reset the FCC1/ATM1 PHYS */
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#define CM_RST_ATM2RST __BIT(4) /* Reset the FCC2/ATM2 PHY */
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#define CM_RST_MEMRST __BIT(3) /* Reset the memory devices on the daughter card */
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#define CM_RST_UTRST __BIT(2) /* Reset the TCOM/ECOM boards */
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#define CM_RST_HRESET __BIT(1) /* Assert HRESET */
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#define CM_RST_SRESET __BIT(0) /* Assert SRESET */
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#define CM_LED 0x05 /* LED data register */
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#define CM_PCI 0x06 /* PCI control/status register */
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#define CM_PCI_M66O __BIT(7)
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#define CM_PCI_PCIXCO __BIT(6)
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#define CM_PCI_M66S __BIT(5) /* PCI V2.3 mode or earlier running at 66MHz */
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#define CM_PCI_DUAL __BIT(4) /* Daughter card has selected dual PCI-mode */
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#define CM_PCI_PSPEED __BITS(2,3) /* detected PCI speed */
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#define CM_PCI_PSPEED_33 __SHIFTIN(0, CM_PCI_PSPEED)
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#define CM_PCI_PSPEED_66 __SHIFTIN(1, CM_PCI_PSPEED)
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#define CM_PCI_PCIX __BIT(1) /* the PCI edge connector is connected to a PCI-X backplace */
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#define CM_PCI_PCIEN __BIT(0) /* if 1, the PCI backplane is not present */
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#define CM_DMA 0x07 /* DMA control register */
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#define CM_DMA_DMARQ0 __BIT(6)
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#define CM_DMA_DMACK0 __BIT(5)
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#define CM_DMA_DMADN0 __BIT(4)
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#define CM_DMA_DMARQ1 __BIT(2)
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#define CM_DMA_DMACK1 __BIT(1)
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#define CM_DMA_DMADN1 __BIT(0)
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#endif /* !_MPC85XX_CADMUSREG_H_ */
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