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289 lines
7.0 KiB
ArmAsm
289 lines
7.0 KiB
ArmAsm
/* $NetBSD: mpc85xx_start.S,v 1.9 2014/08/10 18:01:29 joerg Exp $ */
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/*-
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* Copyright (c) 2010, 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Raytheon BBN Technologies Corp and Defense Advanced Research Projects
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* Agency and which was developed by Matt Thomas of 3am Software Foundry.
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*
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* This material is based upon work supported by the Defense Advanced Research
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* Projects Agency and Space and Naval Warfare Systems Center, Pacific, under
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* Contract No. N66001-09-C-2073.
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* Approved for Public Release, Distribution Unlimited
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <powerpc/asm.h>
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RCSID("$NetBSD: mpc85xx_start.S,v 1.9 2014/08/10 18:01:29 joerg Exp $")
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#include "opt_altivec.h"
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#include "opt_ddb.h"
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#include "opt_ipkdb.h"
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#include "opt_lockdebug.h"
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#include "opt_modular.h"
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#include "opt_multiprocessor.h"
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#include "opt_ppcarch.h"
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#include "opt_ppcparam.h"
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#include "ksyms.h"
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#include <sys/param.h>
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#include <powerpc/spr.h>
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#include <powerpc/trap.h>
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#include <powerpc/psl.h>
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#include <powerpc/booke/pte.h>
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#include <powerpc/booke/spr.h>
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#define LBC_PRIVATE
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#include <powerpc/booke/e500reg.h>
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#include "assym.h"
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#define INTSTK 0
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.text
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.globl _C_LABEL(kernel_text)
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_C_LABEL(kernel_text):
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.globl __start
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__start:
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/*
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* Startup entry. Note, this must be the first thing in the text segment!
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*/
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mr %r8,%r6 /* cmdline (char *) */
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mr %r7,%r5 /* consdev (char *) */
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mr %r6,%r4 /* os_hdr * */
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mr %r5,%r3 /* board info * */
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#ifdef DEBUG
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/*
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* Set all the registers we don't care about to a known junk value.
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*/
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lis %r2,0xdeadbeef@h
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ori %r2,%r2,0xdeadbeef@l
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mr %r9,%r2
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mr %r10,%r9
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mr %r11,%r9
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mr %r12,%r9
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mr %r13,%r9
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mr %r14,%r9
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mr %r15,%r9
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mr %r16,%r9
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mr %r17,%r9
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mr %r18,%r9
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mr %r19,%r9
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mr %r20,%r9
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mr %r21,%r9
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mr %r22,%r9
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mr %r23,%r9
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mr %r24,%r9
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mr %r25,%r9
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mr %r26,%r9
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mr %r27,%r9
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mr %r28,%r9
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mr %r29,%r9
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mr %r30,%r9
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mr %r31,%r9
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#endif /* DEBUG */
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li %r0,0
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mtmsr %r0 /* Disable FPU/MMU/exceptions */
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isync
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/* get start of bss */
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lis %r15,_C_LABEL(_edata)-4@ha
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addi %r15,%r15,_C_LABEL(_edata)-4@l
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/* get end of kernel memory */
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lis %r16,_C_LABEL(end)@ha
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addi %r16,%r16,_C_LABEL(end)@l
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/* zero bss */
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sub %r17,%r16,%r15
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addi %r17,%r17,3+USPACE
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rlwinm %r3,%r17,32-2,2,31 /* srwl %r3,%r17,2 */
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mtctr %r3
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li %r0,0
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2: stwu %r0,4(%r15)
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bdnz 2b
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#if NKSYMS || defined(DDB) || defined(MODULAR)
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/* If we had symbol table location we'd store it here and would've adjusted r8 here */
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lis %r17,_C_LABEL(startsym)@ha
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stw %r18,_C_LABEL(startsym)@l(%r17)
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lis %r17,_C_LABEL(endsym)@ha
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stw %r18,_C_LABEL(endsym)@l(%r17)
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#endif
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/* Set kernel MMU context. */
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li %r0,KERNEL_PID
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mtpid %r0
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isync
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INIT_CPUINFO(16,1,18,17) /* r16 has &_end */
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mr %r4,%r16 /* remember kernelend */
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mtsprg2 %r13 /* r13 has &lwp0, put into sprg2 */
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GET_CPUINFO(%r17)
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addi %r17,%r17,CI_SAVELIFO
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mtsprg3 %r17
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mr %r18,%r31 /* make deadbeef again */
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mr %r17,%r31 /* make deadbeef again */
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mr %r16,%r31 /* make deadbeef again */
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mr %r15,%r31 /* make deadbeef again */
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#if defined(GXEMUL)
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/*
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* This is used to step through the external interrupt vector
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* to validate it.
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*/
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lis %r29,3f@ha
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addi %r29,%r29,3f@l
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mtsrr0 %r29
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mfmsr %r0
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mtsrr1 %r0
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lis %r31,0xdeadf231@ha
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addi %r31,%r31,0xdeadf231@l
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mtlr %r31
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addi %r31,%r31,-0x10
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mtcr %r31
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addi %r31,%r31,-0x10
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mtctr %r31
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addi %r31,%r31,-0x10
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mtxer %r31
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addi %r31,%r31,-0x10
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addi %r30,%r31,-0x10
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addi %r29,%r30,-0x10
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addi %r28,%r29,-0x10
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addi %r27,%r28,-0x10
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addi %r26,%r27,-0x10
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addi %r25,%r26,-0x10
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addi %r24,%r25,-0x10
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addi %r23,%r24,-0x10
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addi %r22,%r23,-0x10
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addi %r21,%r22,-0x10
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addi %r20,%r21,-0x10
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addi %r19,%r20,-0x10
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addi %r18,%r19,-0x10
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addi %r17,%r18,-0x10
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addi %r16,%r17,-0x10
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addi %r15,%r16,-0x10
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addi %r14,%r15,-0x10
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addi %r13,%r14,-0x10
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addi %r12,%r13,-0x10
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addi %r11,%r12,-0x10
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addi %r10,%r11,-0x10
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addi %r9,%r10,-0x10
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addi %r8,%r9,-0x10
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addi %r7,%r8,-0x10
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addi %r6,%r7,-0x10
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addi %r5,%r6,-0x10
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addi %r4,%r5,-0x10
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addi %r3,%r4,-0x10
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addi %r2,%r3,-0x10
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/* leave r1 alone */
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addi %r0,%r2,-0x20
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b _C_LABEL(instruction_tlb_error_vector)
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//b _C_LABEL(program_vector)
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//b _C_LABEL(external_input_vector)
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3:
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#endif
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/*
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* TB is 50Mhz, watchdog should be ~10 seconds which makes that
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* 500 million or 0x20000000. Since it takes 3 bit transitions
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* we really want 0x10000000. That's bit 63-28 or 35. This
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* means we want WPEXT,WP to be 0b10_0011.
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*/
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lis %r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@ha
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addi %r3,%r3,(TCR_WRC_RESET|TCR_WP_2_N(0x23))@l
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mtspr SPR_TCR, %r3
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li %r0, 0
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mtspr SPR_TBL, %r0
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mtspr SPR_TBU, %r0
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mtspr SPR_DBCR0, %r0
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#if 0
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/*
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* Force all dirty lines in the kernel area to memory.
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*/
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lis %r9,kernel_text@ha
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addi %r9,%r9,kernel_text@l
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4: dcbst %r0,%r9
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addi %r9,%r9,32
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cmplw %r9,%r4
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blt %cr0,4b
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mbar 1
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msync
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/*
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* Turn off the data cache, and then invalidate it.
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*/
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li %r3, 0
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mtspr SPR_L1CSR0, %r3
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li %r3, L1CSR_CFI
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mtspr SPR_L1CSR0, %r3
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#endif
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#if 1
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/*
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* Clear any locks from the data or instruction caches.
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*/
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mfspr %r3, SPR_L1CSR0
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ori %r3, %r3, L1CSR_CLFR
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mtspr SPR_L1CSR0, %r3
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mfspr %r3, SPR_L1CSR1
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ori %r3, %r3, L1CSR_CLFR
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mtspr SPR_L1CSR1, %r3
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#endif
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lis %r3,__start@ha
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addi %r3,%r3,__start@l
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bl _C_LABEL(initppc)
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bl _C_LABEL(main)
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loop: b loop /* XXX not reached */
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#include <powerpc/booke/trap_subr.S>
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#include <powerpc/powerpc/locore_subr.S>
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#include <powerpc/powerpc/pio_subr.S>
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#ifdef PPC_HAVE_SPE
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#include <powerpc/booke/spe_subr.S>
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#endif
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#if defined(MULTIPROCESSOR)
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#include <powerpc/booke/e500_mpsubr.S>
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#endif
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#if 0
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.p2align 5
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ENTRY(tlbwe)
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isync
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tlbwe
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isync
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blr
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#endif
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