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289 lines
6.1 KiB
NASM
289 lines
6.1 KiB
NASM
; $NetBSD: arm.asm,v 1.9 2010/04/06 16:20:28 nonaka Exp $
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;
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; Copyright (c) 2001 The NetBSD Foundation, Inc.
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; All rights reserved.
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;
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; This code is derived from software contributed to The NetBSD Foundation
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; by UCHIYAMA Yasushi.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions
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; are met:
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; 1. Redistributions of source code must retain the above copyright
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; notice, this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright
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; notice, this list of conditions and the following disclaimer in the
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; documentation and/or other materials provided with the distribution.
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;
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; THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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; ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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; TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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; PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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; BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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; POSSIBILITY OF SUCH DAMAGE.
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;
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;
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;armasm.exe $(InputPath)
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;arm.obj
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;
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; dummy buffer for WritebackDCache
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EXPORT |dcachesize| [DATA]
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EXPORT |dcachebuf| [DATA]
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AREA |.data|, DATA
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|dcachesize|
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DCD 8192 ; for SA1100
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|dcachebuf|
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% 65536 ; max D-cache size
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AREA |.text|, CODE, PIC
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;
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; Operation mode ops.
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;
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EXPORT |SetSVCMode|
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|SetSVCMode| PROC
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0x13
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetSVCMode|
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EXPORT |SetSystemMode|
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|SetSystemMode| PROC
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mrs r0, cpsr
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orr r0, r0, #0x1f
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetSystemMode|
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;
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; Interrupt ops.
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;
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EXPORT |DI|
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|DI| PROC
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mrs r0, cpsr
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orr r0, r0, #0xc0
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msr cpsr, r0
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mov pc, lr
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ENDP ; |DI|
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EXPORT |EI|
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|EI| PROC
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mrs r0, cpsr
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bic r0, r0, #0xc0
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msr cpsr, r0
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mov pc, lr
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ENDP ; |EI|
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;
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; Cache ops.
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;
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EXPORT |InvalidateICache|
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|InvalidateICache| PROC
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; c7 (CRn) Cache Control Register
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; c5, 0 (CRm, opcode_2) Flush I
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c5, 0
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mov pc, lr
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ENDP ; |InvalidateICache|
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EXPORT |WritebackDCache|
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|WritebackDCache| PROC
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ldr r0, [pc, #24] ; dcachebuf
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ldr r1, [pc, #24]
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ldr r1, [r1] ; dcache-size
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add r1, r1, r0
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|wbdc1|
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ldr r2, [r0], #32 ; line-size is 32byte.
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teq r1, r0
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bne |wbdc1|
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mov pc, lr
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DCD |dcachebuf|
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DCD |dcachesize|
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ENDP ; |WritebackDCache|
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EXPORT |InvalidateDCache|
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|InvalidateDCache| PROC
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; c7 (CRn) Cache Control Register
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; c6, 0 (CRm, opcode_2) Flush D
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c6, 0
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mov pc, lr
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ENDP ; |InvalidateDCache|
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EXPORT |WritebackInvalidateDCache|
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|WritebackInvalidateDCache| PROC
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ldr r0, [pc, #28] ; dcachebuf
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ldr r1, [pc, #28]
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ldr r1, [r1] ; dcache-size
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add r1, r1, r0
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|wbidc1|
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ldr r2, [r0], #32
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teq r1, r0
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bne |wbidc1|
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mcr p15, 0, r0, c7, c6, 0
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mov pc, lr
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DCD |dcachebuf|
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DCD |dcachesize|
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ENDP ; |WritebackInvalidateDCache|
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;
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; WriteBuffer ops
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;
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EXPORT |WritebufferFlush|
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|WritebufferFlush| PROC
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; c7 (CRn) Cache Control Register
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; c10, 4(CRm, opcode_2) Flush D
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; r0 (Rd) ignored
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mcr p15, 0, r0, c7, c10, 4
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mov pc, lr
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ENDP ; |WritebufferFlush|
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;
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; TLB ops.
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;
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EXPORT |FlushIDTLB|
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|FlushIDTLB| PROC
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mcr p15, 0, r0, c8, c7, 0
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mov pc, lr
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ENDP ; |FlushIDTLB|
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EXPORT |FlushITLB|
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|FlushITLB| PROC
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mcr p15, 0, r0, c8, c5, 0
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mov pc, lr
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ENDP ; |FlushITLB|
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EXPORT |FlushDTLB|
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|FlushDTLB| PROC
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mcr p15, 0, r0, c8, c6, 0
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mov pc, lr
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ENDP ; |FlushITLB|
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EXPORT |FlushDTLBS|
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|FlushDTLBS| PROC
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mcr p15, 0, r0, c8, c6, 1
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mov pc, lr
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ENDP ; |FlushITLBS|
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;
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; CurrentProgramStatusRegister access.
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;
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EXPORT |GetCPSR|
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|GetCPSR| PROC
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mrs r0, cpsr
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mov pc, lr
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ENDP ; |GetCPSR|
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EXPORT |SetCPSR|
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|SetCPSR| PROC
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msr cpsr, r0
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mov pc, lr
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ENDP ; |SetCPSR|
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;
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; SA-1100 Coprocessor15 access.
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;
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; Reg0 ID (R)
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EXPORT |GetCop15Reg0|
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|GetCop15Reg0| PROC
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mrc p15, 0, r0, c0, c0, 0
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; 0x4401a119 (44|01 = version 4|A11 = SA1100|9 = E stepping)
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mov pc, lr
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ENDP ; |GetCop15Reg0|
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; Reg1 Control (R/W)
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EXPORT |GetCop15Reg1|
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|GetCop15Reg1| PROC
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mrc p15, 0, r0, c1, c0, 0
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; 0xc007327f (||...........|||..||..|..|||||||)
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; 0 (1)MMU enabled
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; 1 (1)Address fault enabled
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; 2 (1)D-cache enabled
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; 3 (1)Write-buffer enabled
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; 7 (0)little-endian
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; 8 (0)MMU protection (System)
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; 9 (1)MMU protection (ROM)
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; 12 (1)I-cache enabled
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; 13 (1)Base address of interrupt vector is 0xffff0000
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mov pc, lr
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ENDP ; |GetCop15Reg1|
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EXPORT |SetCop15Reg1|
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|SetCop15Reg1| PROC
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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mov pc, lr
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ENDP ; |SetCop15Reg1|
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; Reg2 Translation table base (R/W)
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EXPORT |GetCop15Reg2|
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|GetCop15Reg2| PROC
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mrc p15, 0, r0, c2, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg2|
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EXPORT |SetCop15Reg2|
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|SetCop15Reg2| PROC
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mcr p15, 0, r0, c2, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg2|
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; Reg3 Domain access control (R/W)
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EXPORT |GetCop15Reg3|
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|GetCop15Reg3| PROC
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mrc p15, 0, r0, c3, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg3|
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EXPORT |SetCop15Reg3|
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|SetCop15Reg3| PROC
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mcr p15, 0, r0, c3, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg3|
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; Reg5 Fault status (R/W)
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EXPORT |GetCop15Reg5|
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|GetCop15Reg5| PROC
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mrc p15, 0, r0, c5, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg5|
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; Reg6 Fault address (R/W)
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EXPORT |GetCop15Reg6|
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|GetCop15Reg6| PROC
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mrc p15, 0, r0, c6, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg6|
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; Reg7 Cache operations (W)
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; -> Cache ops
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; Reg8 TLB operations (Flush) (W)
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; -> TLB ops
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; Reg9 Read buffer operations (W)
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; Reg13 Process ID (R/W)
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EXPORT |GetCop15Reg13|
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|GetCop15Reg13| PROC
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mrc p15, 0, r0, c13, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg13|
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EXPORT |SetCop15Reg13|
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|SetCop15Reg13| PROC
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mcr p15, 0, r0, c13, c0, 0
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mov pc, lr
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ENDP ; |SetCop15Reg13|
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; Reg14 Breakpoint (R/W)
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EXPORT |GetCop15Reg14|
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|GetCop15Reg14| PROC
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mrc p15, 0, r0, c14, c0, 0
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mov pc, lr
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ENDP ; |GetCop15Reg14|
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; Reg15 Test, clock, and idle (W)
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END
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