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74 lines
2.8 KiB
C
74 lines
2.8 KiB
C
/* $NetBSD: 7707.h,v 1.6 2008/04/28 20:23:20 martin Exp $ */
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/*-
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* Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPCBOOT_SH_CPU_7707_H_
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#define _HPCBOOT_SH_CPU_7707_H_
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#define SH7707_LCDAR 0xa40000c0 /* address register */
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#define SH7707_LCDDR 0xa40000c2 /* display control register */
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#define SH7707_LCDPR 0xa40000c6 /* palette register */
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#define SH7707_LCDDMR 0xa40000ce /* DMA control register */
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#define SH7707_LCDAR_LCDDMR0 0x0
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#define SH7707_LCDAR_LCDDMR1 0x1
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#define SH7707_LCDAR_LCDDMR2 0x2
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#define SH7707_LCDAR_LCDDMR3 0x3
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#define SH7707_LCDAR_LCDDMR4 0x4
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#define SH7707_CACHE_LINESZ 16
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#define SH7707_CACHE_ENTRY 128
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#define SH7707_CACHE_WAY 4 /* 2-way in RAM mode */
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#define SH7707_CACHE_SIZE \
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(SH7707_CACHE_LINESZ * SH7707_CACHE_ENTRY * SH7707_CACHE_WAY)
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#define SH7707_CACHE_ENTRY_SHIFT 4
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#define SH7707_CACHE_ENTRY_MASK 0x000007f0
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#define SH7707_CACHE_WAY_SHIFT 11
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#define SH7707_CACHE_WAY_MASK 0x00001800
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#define SH7707_CACHE_FLUSH() \
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__BEGIN_MACRO \
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uint32_t __e, __w, __wa, __a; \
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\
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for (__w = 0; __w < SH7707_CACHE_WAY; __w++) { \
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__wa = SH3_CCA | __w << SH7707_CACHE_WAY_SHIFT; \
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for (__e = 0; __e < SH7707_CACHE_ENTRY; __e++) { \
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__a = __wa |(__e << SH7707_CACHE_ENTRY_SHIFT); \
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_reg_read_4(__a) &= ~0x3; /* Clear U,V bit */ \
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} \
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} \
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__END_MACRO
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#define SH7707_MMU_DISABLE SH3_MMU_DISABLE
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#endif // _HPCBOOT_SH_CPU_7707_H_
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