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375 lines
12 KiB
C++
375 lines
12 KiB
C++
/* -*-C++-*- $NetBSD: sh.h,v 1.5 2008/04/28 20:23:20 martin Exp $ */
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/*-
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* Copyright (c) 2001, 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _HPCBOOT_SH_DEV_SH_H_
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#define _HPCBOOT_SH_DEV_SH_H_
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/*
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* SH3, SH4 embeded devices.
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*/
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/*
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* INTC
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*/
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/* SH7709/7709A */
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/* R/W 16bit */
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#define SH3_ICR0 0xfffffee0
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#define SH3_ICR1 0xa4000010
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#define SH3_ICR2 0xa4000012
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#define SH3_PINTER 0xa4000014
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#define SH3_IPRA 0xfffffee2
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#define SH3_IPRB 0xfffffee4
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#define SH3_IPRC 0xa4000016
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#define SH3_IPRD 0xa4000018
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#define SH3_IPRE 0xa400001a
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/* R/W 8bit */
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#define SH3_IRR0 0xa4000004
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/* R 8bit */
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#define SH3_IRR1 0xa4000006
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#define SH3_IRR2 0xa4000008
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#define SH3_ICR0_NMIL 0x8000
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#define SH3_ICR0_NMIE 0x0100
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#define SH3_ICR1_MAI 0x8000
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#define SH3_ICR1_IRQLVL 0x4000
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#define SH3_ICR1_BLMSK 0x2000
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#define SH3_ICR1_IRLSEN 0x1000
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#define SH3_ICR1_IRQ51S 0x0800
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#define SH3_ICR1_IRQ50S 0x0400
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#define SH3_ICR1_IRQ41S 0x0200
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#define SH3_ICR1_IRQ40S 0x0100
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#define SH3_ICR1_IRQ31S 0x0080
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#define SH3_ICR1_IRQ30S 0x0040
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#define SH3_ICR1_IRQ21S 0x0020
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#define SH3_ICR1_IRQ20S 0x0010
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#define SH3_ICR1_IRQ11S 0x0008
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#define SH3_ICR1_IRQ10S 0x0004
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#define SH3_ICR1_IRQ01S 0x0002
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#define SH3_ICR1_IRQ00S 0x0001
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#define SH3_SENSE_SELECT_MASK 0x3
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#define SH3_SENSE_SELECT_FALLING_EDGE 0x0
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#define SH3_SENSE_SELECT_RAISING_EDGE 0x1
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#define SH3_SENSE_SELECT_LOW_LEVEL 0x2
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#define SH3_SENSE_SELECT_RESERVED 0x3
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#define SH3_ICR2_PINT15S 0x8000
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#define SH3_ICR2_PINT14S 0x4000
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#define SH3_ICR2_PINT13S 0x2000
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#define SH3_ICR2_PINT12S 0x1000
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#define SH3_ICR2_PINT11S 0x0800
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#define SH3_ICR2_PINT10S 0x0400
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#define SH3_ICR2_PINT9S 0x0200
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#define SH3_ICR2_PINT8S 0x0100
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#define SH3_ICR2_PINT7S 0x0080
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#define SH3_ICR2_PINT6S 0x0040
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#define SH3_ICR2_PINT5S 0x0020
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#define SH3_ICR2_PINT4S 0x0010
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#define SH3_ICR2_PINT3S 0x0008
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#define SH3_ICR2_PINT2S 0x0004
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#define SH3_ICR2_PINT1S 0x0002
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#define SH3_ICR2_PINT0S 0x0001
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#define SH_IPR_MASK 0xf
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/* SH7750 */
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#define SH4_ICR 0xffd00000
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#define SH4_ICR_NMIL 0x8000
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#define SH4_ICR_MAI 0x4000
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#define SH4_ICR_NMIB 0x0200
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#define SH4_ICR_NMIE 0x0100
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#define SH4_ICR_IRLM 0x0080
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#define SH4_IPRA 0xffd00004
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#define SH4_IPRB 0xffd00008
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#define SH4_IPRC 0xffd0000c
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/* SH7750S */
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#define SH4_IPRD 0xffd00010
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/*
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* Bus State Controller
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*/
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#define SH3_BCR1 0xffffff60
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#define SH3_BCR2 0xffffff62
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#define SH3_WCR1 0xffffff64
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#define SH3_WCR2 0xffffff66
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#define SH3_MCR 0xffffff68
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#define SH3_DCR 0xffffff6a
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#define SH3_PCR 0xffffff6c
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#define SH3_RTCSR 0xffffff6e
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#define SH3_RTCNT 0xffffff70
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#define SH3_RTCOR 0xffffff72
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#define SH3_RFCR 0xffffff74
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#define SH3_BCR3 0xffffff7e
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/*
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* Pin Function Controller
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*/
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#define SH3_PACR 0xa4000100
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#define SH3_PBCR 0xa4000102
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#define SH3_PCCR 0xa4000104
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#define SH3_PDCR 0xa4000106
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#define SH3_PECR 0xa4000108
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#define SH3_PFCR 0xa400010a
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#define SH3_PGCR 0xa400010c
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#define SH3_PHCR 0xa400010e
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#define SH3_PJCR 0xa4000110
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#define SH3_PKCR 0xa4000112
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#define SH3_PLCR 0xa4000114
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#define SH3_SCPCR 0xa4000116
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/*
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* I/O port
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*/
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#define SH3_PADR 0xa4000120
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#define SH3_PBDR 0xa4000122
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#define SH3_PCDR 0xa4000124
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#define SH3_PDDR 0xa4000126
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#define SH3_PEDR 0xa4000128
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#define SH3_PFDR 0xa400012a
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#define SH3_PGDR 0xa400012c
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#define SH3_PHDR 0xa400012e
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#define SH3_PJDR 0xa4000130
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#define SH3_PKDR 0xa4000132
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#define SH3_PLDR 0xa4000134
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#define SH3_SCPDR 0xa4000136
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/*
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* TMU
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*/
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#define SH3_TOCR 0xfffffe90
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#define SH3_TOCR_TCOE 0x01
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#define SH3_TSTR 0xfffffe92
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#define SH3_TSTR_STR2 0x04
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#define SH3_TSTR_STR1 0x02
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#define SH3_TSTR_STR0 0x01
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#define SH3_TCOR0 0xfffffe94
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#define SH3_TCNT0 0xfffffe98
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#define SH3_TCR0 0xfffffe9c
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#define SH3_TCOR1 0xfffffea0
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#define SH3_TCNT1 0xfffffea4
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#define SH3_TCR1 0xfffffea8
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#define SH3_TCOR2 0xfffffeac
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#define SH3_TCNT2 0xfffffeb0
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#define SH3_TCR2 0xfffffeb4
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#define SH3_TCPR2 0xfffffeb8
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#define SH3_TCR_ICPF 0x0200
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#define SH3_TCR_UNF 0x0100
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#define SH3_TCR_ICPE1 0x0080
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#define SH3_TCR_ICPE0 0x0040
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#define SH3_TCR_UNIE 0x0020
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#define SH3_TCR_CKEG1 0x0010
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#define SH3_TCR_CKEG0 0x0008
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#define SH3_TCR_TPSC2 0x0004
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#define SH3_TCR_TPSC1 0x0002
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#define SH3_TCR_TPSC0 0x0001
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#define SH3_TCR_TPSC_P4 0x0000
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#define SH3_TCR_TPSC_P16 0x0001
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#define SH3_TCR_TPSC_P64 0x0002
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#define SH3_TCR_TPSC_P256 0x0003
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/*
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* SCI
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*/
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#define SH4_SCSMR 0xffe00000
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#define SH4_SCBRR 0xffe00004
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#define SH4_SCSCR 0xffe00008
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#define SH4_SCTDR 0xffe0000c
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#define SH4_SCSSR 0xffe00010
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#define SH4_SCRDR 0xffe00014
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#define SH3_SCRSR /* can't access from CPU */
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#define SH3_SCTSR /* can't access from CPU */
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#define SH3_SCSMR 0xfffffe80
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#define SH3_SCBRR 0xfffffe82
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#define SH3_SCSCR 0xfffffe84
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#define SH3_SCTDR 0xfffffe86
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#define SH3_SCSSR 0xfffffe88
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#define SH3_SCRDR 0xfffffe8a
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#define SH3_SCPCR 0xa4000116
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#define SH3_SCPDR 0xa4000136
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#define SCSSR_TDRE 0x80
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#define SH3_SCI_TX_BUSY() \
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while ((_reg_read_1(SH3_SCSSR) & SCSSR_TDRE) == 0)
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#define SH3_SCI_PUTC(c) \
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__BEGIN_MACRO \
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SH3_SCI_TX_BUSY(); \
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_reg_write_1(SH3_SCTDR, c); \
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_reg_write_1(SH3_SCSSR, \
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_reg_read_1(SH3_SCSSR) & ~SCSSR_TDRE); \
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__END_MACRO
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#define SH3_SCI_PRINT(s) \
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__BEGIN_MACRO \
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char *__s =(char *)(s); \
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int __i; \
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for (__i = 0; __s[__i] != '\0'; __i++) { \
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char __c = __s[__i]; \
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if (__c == '\n') \
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SH3_SCI_PUTC('\r'); \
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SH3_SCI_PUTC(__c); \
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} \
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__END_MACRO
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/*
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* SCIF
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*/
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#define SH4_SCSMR2 0xffe80000
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#define SH4_SCBRR2 0xffe80004
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#define SH4_SCSCR2 0xffe80008
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#define SH4_SCFTDR2 0xffe8000c
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#define SH4_SCFSR2 0xffe80010
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#define SH4_SCFRDR2 0xffe80014
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#define SH4_SCFCR2 0xffe80018
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#define SH4_SCFDR2 0xffe8001c
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#define SH4_SCSPTR2 0xffe80020
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#define SH4_SCLSR2 0xffe80024
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#define SH4_SCSMR2 0xffe80000
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#define SH4_SCBRR2 0xffe80004
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#define SH4_SCSCR2 0xffe80008
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#define SH4_SCFTDR2 0xffe8000c
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#define SH4_SCFSR2 0xffe80010
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#define SH4_SCFRDR2 0xffe80014
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#define SH4_SCFCR2 0xffe80018
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#define SH4_SCFDR2 0xffe8001c
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#define SH4_SCSPTR2 0xffe80020
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#define SH4_SCLSR2 0xffe80024
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#define SH4_SCSSR2 SH4_SCFSR2
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#define SH4_SCSSR2 SH4_SCFSR2
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#define SH3_SCSMR2 0xa4000150 /* R/W */
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#define SH3_SCBRR2 0xa4000152 /* R/W */
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#define SH3_SCSCR2 0xa4000154 /* R/W */
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#define SH3_SCFTDR2 0xa4000156 /* W */
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#define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */
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#define SH3_SCFRDR2 0xa400015a /* R */
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#define SH3_SCFCR2 0xa400015c /* R/W */
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#define SH3_SCFDR2 0xa400015e /* R */
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#define SH3_SCSMR2 0xa4000150 /* R/W */
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#define SH3_SCBRR2 0xa4000152 /* R/W */
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#define SH3_SCSCR2 0xa4000154 /* R/W */
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#define SH3_SCFTDR2 0xa4000156 /* W */
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#define SH3_SCSSR2 0xa4000158 /* R/W(0 write only) */
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#define SH3_SCFRDR2 0xa400015a /* R */
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#define SH3_SCFCR2 0xa400015c /* R/W */
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#define SH3_SCFDR2 0xa400015e /* R */
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#define SCSCR2_TIE 0x0080 /* Transmit Interrupt Enable */
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#define SCSCR2_RIE 0x0040 /* Receive Interrupt Enable */
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#define SCSCR2_TE 0x0020 /* Transmit Enable */
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#define SCSCR2_RE 0x0010 /* Receive Enable */
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#define SCSCR2_CKE1 0x0002 /* ClocK Enable 1 */
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#define SCSCR2_CKE0 0x0001 /* ClocK Enable 0 */
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#define SCSCR2_CKE 0x0003 /* ClocK Enable mask */
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#define SCSSR2_ER 0x0080 /* ERror */
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#define SCSSR2_TEND 0x0040 /* Transmit END */
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#define SCSSR2_TDFE 0x0020 /* Transmit Data Fifo Empty */
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#define SCSSR2_BRK 0x0010 /* BReaK detection */
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#define SCSSR2_FER 0x0008 /* Framing ERror */
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#define SCSSR2_PER 0x0004 /* Parity ERror */
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#define SCSSR2_RDF 0x0002 /* Receive fifo Data Full */
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#define SCSSR2_DR 0x0001 /* Data Ready */
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#define SCFCR2_RTRG1 0x0080 /* Receive TRiGger 1 */
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#define SCFCR2_RTRG0 0x0040 /* Receive TRiGger 0 */
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#define SCFCR2_TTRG1 0x0020 /* Transmit TRiGger 1 */
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#define SCFCR2_TTRG0 0x0010 /* Transmit TRiGger 0 */
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#define SCFCR2_MCE 0x0008 /* Modem Control Enable */
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#define SCFCR2_TFRST 0x0004 /* Transmit Fifo register ReSeT */
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#define SCFCR2_RFRST 0x0002 /* Receive Fifo register ReSeT */
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#define SCFCR2_LOOP 0x0001 /* LOOP back test */
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#define FIFO_RCV_TRIGGER_1 0x0000
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#define FIFO_RCV_TRIGGER_4 0x0040
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#define FIFO_RCV_TRIGGER_8 0x0080
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#define FIFO_RCV_TRIGGER_14 0x00c0
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#define FIFO_XMT_TRIGGER_8 0x0000
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#define FIFO_XMT_TRIGGER_4 0x0010
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#define FIFO_XMT_TRIGGER_2 0x0020
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#define FIFO_XMT_TRIGGER_1 0x0030
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#define SCFDR2_TXCNT 0xff00 /* Tx CouNT */
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#define SCFDR2_RECVCNT 0x00ff /* Rx CouNT */
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#define SCFDR2_TXF_FULL 0x1000 /* Tx FULL */
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#define SCFDR2_RXF_EPTY 0x0000 /* Rx EMPTY */
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#define SCSMR2_CHR 0x40 /* Character length */
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#define SCSMR2_PE 0x20 /* Parity enable */
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#define SCSMR2_OE 0x10 /* Parity mode */
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#define SCSMR2_STOP 0x08 /* Stop bit length */
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#define SCSMR2_CKS 0x03 /* Clock select */
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/* simple serial console macros. */
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#define SH3_SCIF_TX_BUSY() \
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while ((_reg_read_2(SH3_SCSSR2) & SCSSR2_TDFE) == 0)
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#define SH3_SCIF_PUTC(c) \
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__BEGIN_MACRO \
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SH3_SCIF_TX_BUSY(); \
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/* wait until previous transmit done. */ \
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_reg_write_1(SH3_SCFTDR2, c); \
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/* Clear transmit FIFO empty flag */ \
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_reg_write_1(SH3_SCSSR2, \
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_reg_read_1(SH3_SCSSR2) & ~(SCSSR2_TDFE | SCSSR2_TEND)); \
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__END_MACRO
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#define SH3_SCIF_PRINT(s) \
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__BEGIN_MACRO \
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char *__s =(char *)(s); \
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int __i; \
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for (__i = 0; __s[__i] != '\0'; __i++) { \
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char __c = __s[__i]; \
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if (__c == '\n') \
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SH3_SCIF_PUTC('\r'); \
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SH3_SCIF_PUTC(__c); \
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} \
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__END_MACRO
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#define SH3_SCIF_PRINT_HEX(h) \
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__BEGIN_MACRO \
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uint32_t __h =(uint32_t)(h); \
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int __i; \
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SH3_SCIF_PUTC('0'); SH3_SCIF_PUTC('x'); \
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for (__i = 0; __i < 8; __i++, __h <<= 4) { \
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int __n =(__h >> 28) & 0xf; \
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char __c = __n > 9 ? 'A' + __n - 10 : '0' + __n; \
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SH3_SCIF_PUTC(__c); \
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} \
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SH3_SCIF_PUTC('\r'); SH3_SCIF_PUTC('\n'); \
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__END_MACRO
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#endif /* _HPCBOOT_SH_DEV_SH_H_ */
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