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166 lines
3.8 KiB
C++
166 lines
3.8 KiB
C++
/* $NetBSD: sh_arch.cpp,v 1.15 2008/04/28 20:23:20 martin Exp $ */
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/*-
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* Copyright (c) 2001, 2002, 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by UCHIYAMA Yasushi.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hpcboot.h>
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#include <hpcmenu.h>
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#include <sh3/sh_arch.h>
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SH_BOOT_FUNC_(7707);
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SH_BOOT_FUNC_(7709);
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SH_BOOT_FUNC_(7709A);
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SH_BOOT_FUNC_(7750);
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static int _cpu_type;
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int
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SHArchitecture::cpu_type()
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{
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if (_cpu_type == 0) {
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#if _WIN32_WCE == 101
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_cpu_type = 3;
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#else
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SYSTEM_INFO si;
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GetSystemInfo(&si);
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_cpu_type = si.wProcessorLevel;
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#endif
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}
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return _cpu_type;
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}
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BOOL
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SHArchitecture::init()
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{
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if (!_mem->init()) {
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DPRINTF((TEXT("can't initialize memory manager.\n")));
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return FALSE;
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}
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// D-RAM information
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DPRINTF((TEXT("Memory Bank:\n")));
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return TRUE;
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}
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void
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SHArchitecture::systemInfo()
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{
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// Windows CE common information.
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super::systemInfo();
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// CPU specific.
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_dev->dump(HPC_MENU._cons_parameter);
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}
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BOOL
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SHArchitecture::setupLoader()
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{
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vaddr_t v;
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if (!_mem->getPage(v , _loader_addr)) {
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DPRINTF((TEXT("can't get page for 2nd loader.\n")));
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return FALSE;
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}
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_loader_addr = ptokv(_loader_addr);
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DPRINTF((TEXT("2nd bootloader address U0: 0x%08x P1: 0x%08x\n"),
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(unsigned)v,(unsigned)_loader_addr));
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memcpy(LPVOID(v), LPVOID(_boot_func), _mem->getPageSize());
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return TRUE;
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}
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void
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SHArchitecture::jump(paddr_t info, paddr_t pvec)
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{
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kaddr_t sp;
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vaddr_t v;
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paddr_t p;
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// stack for bootloader
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_mem->getPage(v, p);
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sp = ptokv(p + _mem->getPageSize() / 2);
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info = ptokv(info);
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pvec = ptokv(pvec);
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DPRINTF((TEXT("boot arg: 0x%08x stack: 0x%08x\nBooting kernel...\n"),
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info, sp));
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// Change to privilege-mode.
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SetKMode(1);
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// Cache flush(for 2nd bootloader)
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//
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// SH4 uses WinCE CacheSync(). this routine may causes TLB
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// exception. so calls before suspendIntr().
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//
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cache_flush();
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// Disable external interrupt.
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suspendIntr();
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// jump to 2nd loader.(run P1) at this time I still use MMU.
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__asm(
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"mov r6, r15\n"
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"jmp @r7\n"
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"nop \n", info, pvec, sp, _loader_addr);
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// NOTREACHED
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}
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// disable external interrupt and save its priority.
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uint32_t
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suspendIntr()
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{
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uint32_t sr;
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__asm(
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"stc sr, r0\n"
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"mov.l r0, @r4\n"
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"or r5, r0\n"
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"ldc r0, sr\n", &sr, 0x000000f0);
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return sr & 0x000000f0;
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}
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// resume external interrupt priority.
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void
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resumeIntr(uint32_t s)
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{
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__asm(
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"stc sr, r0\n"
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"and r5, r0\n"
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"or r4, r0\n"
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"ldc r0, sr\n", s, 0xffffff0f);
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}
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