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135 lines
4.9 KiB
C
135 lines
4.9 KiB
C
/* $NetBSD: geodereg.h,v 1.9 2009/10/19 23:19:38 rmind Exp $ */
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/*-
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* Copyright (c) 2005 David Young. All rights reserved.
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*
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* This code was written by David Young.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY DAVID YOUNG ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DAVID
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* YOUNG BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the AMD Geode SC1100.
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*/
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#ifndef _I386_PCI_GEODEREG_H_
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#define _I386_PCI_GEODEREG_H_
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#include <lib/libkern/libkern.h>
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/* AMD Geode SC1100 X-Bus PCI Configuration Register: General
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* Configuration Block Scratchpad. Set to 0x00000000 after chip reset.
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* The BIOS writes the base address of the General Configuration
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* Block to this register.
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*/
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#define SC1100_XBUS_CBA_SCRATCHPAD 0x64
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#define SC1100_GCB_SIZE 64
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/* watchdog timeout register, 16 bits. */
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#define SC1100_GCB_WDTO 0x00
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/* Watchdog configuration register, 16 bits. */
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#define SC1100_GCB_WDCNFG 0x02
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#define SC1100_WDCNFG_RESERVED __BITS(15,9) /* write as read */
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/* 32kHz clock power-down, 0: clock is enabled, 1: clock is disabled. */
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#define SC1100_WDCNFG_WD32KPD __BIT(8)
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/* Watchdog event type 1, and type 2
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*
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* 00: no action (default after POR# is asserted)
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* 01: interrupt
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* 10: SMI
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* 11: system reset
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*/
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#define SC1100_WDCNFG_WDTYPE2_MASK __BITS(7,6)
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#define SC1100_WDCNFG_WDTYPE1_MASK __BITS(5,4)
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#define SC1100_WDCNFG_WDTYPE2_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE2_MASK)
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#define SC1100_WDCNFG_WDTYPE2_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE2_MASK)
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#define SC1100_WDCNFG_WDTYPE2_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE2_MASK)
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#define SC1100_WDCNFG_WDTYPE2_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE2_MASK)
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#define SC1100_WDCNFG_WDTYPE1_NOACTION __SHIFTIN(0, SC1100_WDCNFG_WDTYPE1_MASK)
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#define SC1100_WDCNFG_WDTYPE1_INTERRUPT __SHIFTIN(1, SC1100_WDCNFG_WDTYPE1_MASK)
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#define SC1100_WDCNFG_WDTYPE1_SMI __SHIFTIN(2, SC1100_WDCNFG_WDTYPE1_MASK)
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#define SC1100_WDCNFG_WDTYPE1_RESET __SHIFTIN(3, SC1100_WDCNFG_WDTYPE1_MASK)
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/* Watchdog timer prescaler
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*
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* The prescaler divisor is 2**WDPRES. 1110 (0xe) and 1111 (0xf) are
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* reserved values.
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*/
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#define SC1100_WDCNFG_WDPRES_MASK __BITS(3,0)
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#define SC1100_WDCNFG_WDPRES_MAX 0xd
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/* Watchdog status register, 8 bits. */
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#define SC1100_GCB_WDSTS 0x04
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#define SC1100_WDSTS_RESERVED __BIT(7,4) /* write as read */
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/* Set to 1 when watchdog reset is asserted. Read-only. Reset either by
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* POR# (power-on reset) or by writing 0 to WDOVF.
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*/
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#define SC1100_WDSTS_WDRST __BIT(3)
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/* Set to 1 when watchdog SMI is asserted. Read-only. Reset either by
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* POR# (power-on reset) or by writing 0 to WDOVF.
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*/
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#define SC1100_WDSTS_WDSMI __BIT(2)
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/* Set to 1 when watchdog interrupt is asserted. Read-only. Reset either by
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* POR# (power-on reset) or by writing 0 to WDOVF.
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*/
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#define SC1100_WDSTS_WDINT __BIT(1)
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/* Set to 1 when watchdog overflow is asserted. Reset either by
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* POR# (power-on reset) or by writing 1 to this bit.
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*/
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#define SC1100_WDSTS_WDOVF __BIT(0)
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/*
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* Helpful constants
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*/
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/* maximum watchdog interval in seconds */
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#define SC1100_WDIVL_MAX ((1 << SC1100_WDCNFG_WDPRES_MAX) * \
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UINT16_MAX / SC1100_WDCLK_HZ)
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/* watchdog clock rate in Hertz */
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#define SC1100_WDCLK_HZ 32000
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/*
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* high resolution timer
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*/
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#define SC1100_GCB_TMVALUE_L 0x08 /* timer value */
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#define SC1100_GCB_TMSTS_B 0x0c /* status */
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#define SC1100_TMSTS_OVFL __BIT(0) /* set: overflow */
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#define SC1100_GCB_TMCNFG_B 0x0d /* configuration */
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#define SC1100_TMCNFG_TM27MPD __BIT(2) /* set: power down on SUSPA# */
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#define SC1100_TMCNFG_TMCLKSEL __BIT(1) /* set: 27MHz clock, clear: 1MHz */
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#define SC1100_TMCNFG_TMEN __BIT(0) /* set: timer interrupt enabled */
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#define SC1100_GCB_IID_B 0x3c /* chip identification register */
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#define SC1100_GCB_REV_B 0x3d /* revision register */
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#endif /* _I386_PCI_GEODEREG_H_ */
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