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74 lines
1.5 KiB
C
74 lines
1.5 KiB
C
/* $NetBSD: intr.h,v 1.5 2009/07/20 06:14:15 kiyohara Exp $ */
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/* XXX: cherry: To Be fixed when we switch on interrupts. */
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#ifndef _IA64_INTR_H_
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#define _IA64_INTR_H_
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#include <machine/intrdefs.h>
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static __inline int splraise(int dummy) { return 0; }
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static __inline void spllower(int dummy) { }
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/*
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* Miscellaneous
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*/
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#define splvm() splraise(IPL_VM)
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#define splhigh() splraise(IPL_HIGH)
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#define spl0() spllower(IPL_NONE)
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#define splsched() splraise(IPL_SCHED)
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#define spllock() splhigh()
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#define splx(x) spllower(x)
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/*
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* Software interrupt masks
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*/
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#define splsoftclock() splraise(IPL_SOFTCLOCK)
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#define splsoftnet() splraise(IPL_SOFTNET)
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#define splsoftserial() splraise(IPL_SOFTSERIAL)
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typedef int ipl_t;
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typedef struct {
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ipl_t _ipl;
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} ipl_cookie_t;
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static inline ipl_cookie_t
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makeiplcookie(ipl_t ipl)
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{
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return (ipl_cookie_t){._ipl = ipl};
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}
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static inline int
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splraiseipl(ipl_cookie_t icookie)
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{
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return splraise(icookie._ipl);
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}
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/*
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* Layout of the Processor Interrupt Block.
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*/
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struct ia64_interrupt_block
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{
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uint64_t ib_ipi[0x20000]; /* 1Mb of IPI interrupts */
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uint8_t ib_reserved1[0xe0000];
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uint8_t ib_inta; /* Generate INTA cycle */
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uint8_t ib_reserved2[7];
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uint8_t ib_xtp; /* XTP cycle */
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uint8_t ib_reserved3[7];
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uint8_t ib_reserved4[0x1fff0];
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};
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extern uint64_t ia64_lapic_address;
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#define IA64_INTERRUPT_BLOCK \
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(struct ia64_interrupt_block *)IA64_PHYS_TO_RR6(ia64_lapic_address)
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void *intr_establish(int, int, int, int (*)(void *), void *);
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void intr_disestablish(void *);
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#endif /* ! _IA64_INTR_H_ */
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