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125 lines
5.9 KiB
C
125 lines
5.9 KiB
C
/* $NetBSD: ahcireg.h,v 1.1 2007/03/20 08:52:01 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#ifndef _AHCIREG_H
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#define _AHCIREG_H
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#define ADMHCD_REG_CONTROL 0x00
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#define ADMHCD_REG_INTSTATUS 0x04
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#define ADMHCD_REG_INTENABLE 0x08
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#define ADMHCD_REG_HOSTCONTROL 0x10
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#define ADMHCD_REG_FMINTERVAL 0x18
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#define ADMHCD_REG_FMNUMBER 0x1c
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#define ADMHCD_REG_LSTHRESH 0x70
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#define ADMHCD_REG_RHDESCR 0x74
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#define ADMHCD_REG_PORTSTATUS0 0x78
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#define ADMHCD_REG_PORTSTATUS1 0x7c
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#define ADMHCD_REG_HOSTHEAD 0x80
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#define ADMHCD_NUMPORTS 2
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#define ADMHCD_HOST_EN 0x00000001 /* Host enable */
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#define ADMHCD_SW_INTREQ 0x00000002 /* request software int */
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#define ADMHCD_SW_RESET 0x00000008 /* Reset */
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#define ADMHCD_INT_TD 0x00100000 /* TD completed */
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#define ADMHCD_INT_SW 0x20000000 /* software interrupt */
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#define ADMHCD_INT_FATAL 0x40000000 /* Fatal interrupt */
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#define ADMHCD_INT_ACT 0x80000000 /* Interrupt active */
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#define ADMHCD_STATE_RST 0x00000000 /* bus state reset */
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#define ADMHCD_STATE_RES 0x00000001 /* bus state resume */
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#define ADMHCD_STATE_OP 0x00000002 /* bus state operational */
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#define ADMHCD_STATE_SUS 0x00000003 /* bus state suspended */
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#define ADMHCD_DMA_EN 0x00000004 /* enable dma engine */
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#define ADMHCD_NPS 0x00000020 /* No Power Switch */
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#define ADMHCD_LPSC 0x04000000 /* Local power switch change */
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#define ADMHCD_CCS 0x00000001 /* current connect status */
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#define ADMHCD_PES 0x00000002 /* port enable status */
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#define ADMHCD_PSS 0x00000004 /* port suspend status */
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#define ADMHCD_POCI 0x00000008 /* port overcurrent indicator */
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#define ADMHCD_PRS 0x00000010 /* port reset status */
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#define ADMHCD_PPS 0x00000100 /* port power status */
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#define ADMHCD_LSDA 0x00000200 /* low speed device attached */
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#define ADMHCD_CSC 0x00010000 /* connect status change */
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#define ADMHCD_PESC 0x00020000 /* enable status change */
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#define ADMHCD_PSSC 0x00040000 /* suspend status change */
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#define ADMHCD_OCIC 0x00080000 /* overcurrent change*/
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#define ADMHCD_PRSC 0x00100000 /* reset status change */
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struct admhcd_ed {
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/* Don't change first four, they used for DMA */
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volatile u_int32_t control;
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volatile struct admhcd_td *tail;
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volatile struct admhcd_td *head;
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volatile struct admhcd_ed *next;
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/* the rest is for the driver only: */
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u_int32_t unused[4];
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} __attribute__ ((packed));
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#define ADMHCD_ED_EPSHIFT 7 /* Shift for endpoint number */
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#define ADMHCD_ED_INT 0x00000800 /* Is this an int endpoint */
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#define ADMHCD_ED_SPEED 0x00002000 /* Is it a high speed dev? */
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#define ADMHCD_ED_SKIP 0x00004000 /* Skip this ED */
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#define ADMHCD_ED_FORMAT 0x00008000 /* Is this an isoc endpoint */
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#define ADMHCD_ED_MAXSHIFT 16 /* Shift for max packet size */
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struct admhcd_td {
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/* Don't change first four, they are used for DMA */
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volatile u_int32_t control;
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volatile u_int32_t buffer;
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volatile u_int32_t buflen;
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volatile struct admhcd_td *next;
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/* the rest is for the driver only: */
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/* struct urb *urb;
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struct admhcd_td *real; */
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u_int32_t len;
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u_int32_t unused[3];
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} __attribute__ ((packed));
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#define ADMHCD_TD_OWN 0x80000000
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#define ADMHCD_TD_TOGGLE 0x00000000
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#define ADMHCD_TD_DATA0 0x01000000
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#define ADMHCD_TD_DATA1 0x01800000
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#define ADMHCD_TD_OUT 0x00200000
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#define ADMHCD_TD_IN 0x00400000
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#define ADMHCD_TD_SETUP 0x00000000
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#define ADMHCD_TD_ISO 0x00010000
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#define ADMHCD_TD_R 0x00040000
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#define ADMHCD_TD_INTEN 0x00010000
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#define ADMHCD_TD_ERRMASK 0x78000000
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#define ADMHCD_TD_ERRSHIFT 27
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#endif /* _AHCIREG_H */
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