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66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/* $NetBSD: augpioreg.h,v 1.3 2006/02/18 23:21:06 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUGPIOREG_H
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#define _MIPS_ALCHEMY_DEV_AUGPIOREG_H
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#define AUGPIO_NPINS 64
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/*
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* SYS_GPIO registers -- offset from GPIO_BASE.
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*
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* This excludes SYS_PINFUNC, that has to be included in the SYS_BASE
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* registers -- it is surrounded by other non-GPIO related regs.
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*/
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#define AUGPIO_TRIOUTRD 0x00
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#define AUGPIO_TRIOUTCLR 0x00
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#define AUGPIO_OUTPUTRD 0x08
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#define AUGPIO_OUTPUTSET 0x08
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#define AUGPIO_OUTPUTCLR 0x0C
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#define AUGPIO_PINSTATERD 0x10
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#define AUGPIO_PININPUTEN 0x10
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#define AUGPIO_SIZE 0x14
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/* GPIO2 registers -- offset from GPIO2_BASE */
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#define AUGPIO2_DIR 0x00
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#define AUGPIO2_OUTPUT 0x08
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#define AUGPIO2_PINSTATE 0x0C
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#define AUGPIO2_INTEN 0x10
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#define AUGPIO2_ENABLE 0x14
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#define AUGPIO2_SIZE 0x18
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#define AUGPIO_GPIO2_ENABLE_CE 0x1
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#define AUGPIO_GPIO2_ENABLE_MR 0x2
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#endif /* _MIPS_ALCHEMY_DEV_AUPCIREG_H */
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