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145 lines
4.4 KiB
C
145 lines
4.4 KiB
C
/* $NetBSD: aupscreg.h,v 1.3 2006/10/02 07:32:16 gdamore Exp $ */
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/*-
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* Copyright (c) 2006 Shigeyuki Fukushima.
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* All rights reserved.
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*
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* Written by Shigeyuki Fukushima.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUPSCREG_H_
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#define _MIPS_ALCHEMY_DEV_AUPSCREG_H_
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/*
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* PSC registers (offset from PSCn_BASE).
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*/
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/* psc_sel: PSC clock and protocol select
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* CLK [5:4]
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* 00 = pscn_intclk (for SPI, SMBus, I2S Master[PSC3 Only])
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* 01 = PSCn_EXTCLK (for SPI, SMBus, I2S Master)
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* 10 = PSCn_CLK (for AC97, I2S Slave)
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* 11 = Reserved
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* PS [2:0]
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* 000 = Protocol disable
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* 001 = Reserved
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* 010 = SPI mode
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* 011 = I2S mode
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* 100 = AC97 mode
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* 101 = SMBus mode
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* 11x = Reserved
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*/
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#define AUPSC_SEL 0x00 /* R/W */
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# define AUPSC_SEL_CLK(x) ((x & 0x03) << 4) /* CLK */
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# define AUPSC_SEL_PS(x) (x & 0x07)
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# define AUPSC_SEL_DISABLE 0
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# define AUPSC_SEL_SPI 2
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# define AUPSC_SEL_I2S 3
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# define AUPSC_SEL_AC97 4
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# define AUPSC_SEL_SMBUS 5
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/* psc_ctrl: PSC control
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* ENA [1:0]
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* 00 = Disable/Reset
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* 01 = Reserved
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* 10 = Suspend
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* 11 = Enable
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*/
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#define AUPSC_CTRL 0x04 /* R/W */
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# define AUPSC_CTRL_ENA(x) (x & 0x03)
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# define AUPSC_CTRL_DISABLE 0
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# define AUPSC_CTRL_SUSPEND 2
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# define AUPSC_CTRL_ENABLE 3
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/* 0x0008 - 0x002F: Protocol-specific registers */
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/* psc_stat: PSC status
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* DI [1]
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* 1 = Device interrupt
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* DR [1]
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* 1 = Device ready
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* SR [0]
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* 1 = PSC ready
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* all other bits a are protocol specific
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*/
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#define AUPSC_STAT 0x14
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# define AUPSC_STAT_SR 1
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# define AUPSC_STAT_DR 2
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# define AUPSC_STAT_DI 4
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/* PSC registers size */
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#define AUPSC_SIZE 0x2f
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/*
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* SPI Protocol registers
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*/
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#define AUPSC_SPICFG 0x08 /* R/W */
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#define AUPSC_SPIMSK 0x0c /* R/W */
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#define AUPSC_SPIPCR 0x10 /* R/W */
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#define AUPSC_SPISTAT 0x14 /* Read only */
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#define AUPSC_SPIEVNT 0x18 /* R/W */
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#define AUPSC_SPITXRX 0x1c /* R/W */
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/*
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* I2S Protocol registers
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*/
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#define AUPSC_I2SCFG 0x08 /* R/W */
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#define AUPSC_I2SMSK 0x0c /* R/W */
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#define AUPSC_I2SPCR 0x10 /* R/W */
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#define AUPSC_I2SSTAT 0x14 /* Read only */
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#define AUPSC_I2SEVNT 0x18 /* R/W */
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#define AUPSC_I2STXRX 0x1c /* R/W */
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#define AUPSC_I2SUDF 0x20 /* R/W */
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/*
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* AC97 Protocol registers
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*/
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#define AUPSC_AC97CFG 0x08 /* R/W */
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#define AUPSC_AC97MSK 0x0c /* R/W */
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#define AUPSC_AC97PCR 0x10 /* R/W */
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#define AUPSC_AC97STAT 0x14 /* Read only */
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#define AUPSC_AC97EVNT 0x18 /* R/W */
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#define AUPSC_AC97TXRX 0x1c /* R/W */
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#define AUPSC_AC97CDC 0x20 /* R/W */
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#define AUPSC_AC97RST 0x24 /* R/W */
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#define AUPSC_AC97GPO 0x28 /* R/W */
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#define AUPSC_AC97GPI 0x2c /* Read only */
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/*
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* SMBus Protocol registers
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*/
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#define AUPSC_SMBCFG 0x08 /* R/W */
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#define AUPSC_SMBMSK 0x0c /* R/W */
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#define AUPSC_SMBPCR 0x10 /* R/W */
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#define AUPSC_SMBSTAT 0x14 /* Read only */
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#define AUPSC_SMBEVNT 0x18 /* R/W */
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#define AUPSC_SMBTXRX 0x1c /* R/W */
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#define AUPSC_SMBTMR 0x20 /* R/W */
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#endif /* _MIPS_ALCHEMY_DEV_AUPSCREG_H_ */
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