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65 lines
3.2 KiB
C
65 lines
3.2 KiB
C
/* $NetBSD: usbdreg.h,v 1.1 2006/02/09 03:14:31 gdamore Exp $ */
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/*
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* Copyright 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_USBDREG_H
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#define _MIPS_ALCHEMY_DEV_USBDREG_H
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#define USBD_EP0RD 0x00 /* Read from endpoint 0 */
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#define USBD_EP0WR 0x04 /* Write to endpoint 0 */
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#define USBD_EP1WR 0x08 /* Write to endpoint 1 */
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#define USBD_EP2WR 0x0c /* Write to endpoint 2 */
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#define USBD_EP3RD 0x10 /* Read from endpoint 3 */
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#define USBD_EP4RD 0x14 /* Read from endpoint 4 */
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#define USBD_INTEN 0x18 /* Interrupt Enable Register */
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#define USBD_INTSTAT 0x1c /* Interrupt Status Register */
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#define USBD_CONFIG 0x20 /* Write Configuration Register */
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#define USBD_EP0CS 0x24 /* Endpoint 0 control and status */
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#define USBD_EP1CS 0x28 /* Endpoint 1 control and status */
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#define USBD_EP2CS 0x2c /* Endpoint 2 control and status */
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#define USBD_EP3CS 0x30 /* Endpoint 3 control and status */
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#define USBD_EP4CS 0x34 /* Endpoint 4 control and status */
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#define USBD_FRAMENUM 0x38 /* Current frame number */
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#define USBD_EP0RDSTAT 0x40 /* EP0 Read FIFO Status */
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#define USBD_EP0WRSTAT 0x44 /* EP0 Write FIFO Status */
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#define USBD_EP1WRSTAT 0x48 /* EP1 Write FIFO Status */
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#define USBD_EP2WRSTAT 0x4c /* EP2 Write FIFO Status */
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#define USBD_EP3RDSTAT 0x50 /* EP3 Read FIFO Status */
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#define USBD_EP4RDSTAT 0x54 /* EP4 Read FIFO Status */
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#define USBD_ENABLE 0x58 /* USB Device Controller Enable */
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#endif /* _MIPS_ALCHEMY_DEV_USBDREG_H */
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