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288 lines
8.2 KiB
C
288 lines
8.2 KiB
C
/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ar7100.c,v 1.3 2015/06/09 22:50:50 matt Exp $");
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#define __INTR_PRIVATE
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#include "pci.h"
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#include "opt_memsize.h"
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#include <sys/param.h>
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#include <sys/device.h>
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#include <sys/cpu.h>
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#include <prop/proplib.h>
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#include <mips/cpuregs.h>
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#include <mips/atheros/include/platform.h>
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#include <mips/atheros/include/ar9344reg.h>
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#define AR7100_BASE_FREQ (40*1000*1000)
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static const char * const ar7100_cpu_intrnames[] = {
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[AR7100_CPU_IRQ_PCI] = "irq 0 (pci)",
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[ARCHIP_CPU_IRQ_USB] = "irq 1 (usb)",
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[ARCHIP_CPU_IRQ_GMAC0] = "irq 2 (gmac0)",
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[ARCHIP_CPU_IRQ_GMAC1] = "irq 3 (gmac1)",
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[ARCHIP_CPU_IRQ_MISC] = "irq 4 (misc)",
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[ARCHIP_CPU_IRQ_TIMER] = "irq 5 (timer)",
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};
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static const char * const ar7100_misc_intrnames[] = {
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[AR7100_MISC_IRQ_TIMER] = "irq 0 (timer)",
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[AR7100_MISC_IRQ_ERROR] = "irq 1 (error)",
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[AR7100_MISC_IRQ_GPIO] = "irq 2 (gpio)",
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[AR7100_MISC_IRQ_UART0] = "irq 3 (uart)",
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[AR7100_MISC_IRQ_WDOG] = "irq 4 (wdog)",
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[AR7100_MISC_IRQ_PC] = "irq 5 (pc)",
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[AR7100_MISC_IRQ_OHCI] = "irq 6 (ochi)",
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[AR7100_MISC_IRQ_DMA] = "irq 7 (dma)",
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};
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static const struct ipl_sr_map ar7100_ipl_sr_map = {
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.sr_bits = {
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[IPL_NONE] = 0,
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[IPL_SOFTCLOCK] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTBIO] = MIPS_SOFT_INT_MASK_0,
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[IPL_SOFTNET] = MIPS_SOFT_INT_MASK,
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[IPL_SOFTSERIAL] = MIPS_SOFT_INT_MASK,
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[IPL_BIO] = MIPS_SOFT_INT_MASK |
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MIPS_INT_MASK_0 | /* PCI */
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MIPS_INT_MASK_1, /* USB */
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[IPL_NET] = MIPS_SOFT_INT_MASK |
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MIPS_INT_MASK_0 | /* PCI */
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MIPS_INT_MASK_1 | /* USB */
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MIPS_INT_MASK_2 | /* GMAC0 */
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MIPS_INT_MASK_3, /* GMAC1 */
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[IPL_SERIAL] = MIPS_SOFT_INT_MASK |
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MIPS_INT_MASK_0 | /* PCIE RC */
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MIPS_INT_MASK_1 | /* USB */
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MIPS_INT_MASK_2 | /* GMAC0 */
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MIPS_INT_MASK_3 | /* GMAC1 */
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MIPS_INT_MASK_4, /* MISC (UART0/1) */
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[IPL_SCHED] = MIPS_INT_MASK, /* EVERYTHING */
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[IPL_DDB] = MIPS_INT_MASK, /* EVERYTHING */
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[IPL_HIGH] = MIPS_INT_MASK, /* EVERYTHING */
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},
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};
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static void
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ar7100_intr_init(void)
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{
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atheros_intr_init();
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}
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static uint32_t
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ar7100_get_memsize(void)
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{
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#ifdef MEMSIZE
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return MEMSIZE;
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#else
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return 128*1024*1024;
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#endif
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}
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static void
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ar7100_wdog_reload(uint32_t period)
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{
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if (period == 0) {
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PUTRESETREG(ARCHIP_RESET_WDOG_CTL, ARCHIP_WDOG_CTL_IGNORE);
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PUTRESETREG(ARCHIP_RESET_WDOG_TIMER, 0);
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} else {
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PUTRESETREG(ARCHIP_RESET_WDOG_TIMER, period);
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PUTRESETREG(ARCHIP_RESET_WDOG_CTL, ARCHIP_WDOG_CTL_RESET);
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}
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}
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static void
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ar7100_bus_init(void)
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{
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printf("resetctl = %#x\n", GETRESETREG(AR7100_RESET_RESETCTL));
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#if NPCI > 0 && 0
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_0) = 0x10000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_1) = 0x11000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_2) = 0x12000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_3) = 0x13000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_4) = 0x14000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_5) = 0x15000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_6) = 0x16000000;
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REGVAL(ARCHIP_DDR_BASE + AR7100_PCI_WINDOW_7) = 0x07000000;
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#endif
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}
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static void
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ar7100_reset(void)
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{
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PUTRESETREG(AR7100_RESET_RESETCTL, ARCHIP_RESETCTL_FULL_CHIP_RESET);
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}
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static void
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ar7100_get_freqs(struct arfreqs *freqs)
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{
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const uint32_t pll = GETPLLREG(ARCHIP_PLL_CPU_PLL_CONFIG);
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const uint32_t ref_freq = AR7100_BASE_FREQ;
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const uint32_t pll_freq =
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ref_freq * (__SHIFTOUT(pll, AR7100_PLL_PLL_FB) + 1);
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const uint32_t cpu_freq =
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pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_CPU_DIV_SEL) + 1);
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const uint32_t ddr_freq =
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pll_freq / (__SHIFTOUT(pll, AR7100_CPU_PLL_DDR_DIV_SEL) + 1);
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const uint32_t bus_freq =
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cpu_freq / ((__SHIFTOUT(pll, AR7100_CPU_PLL_AHB_DIV) + 1) * 2);
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freqs->freq_bus = bus_freq;
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freqs->freq_cpu = cpu_freq;
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freqs->freq_mem = ddr_freq;
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freqs->freq_pll = pll_freq;
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freqs->freq_ref = ref_freq;
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}
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static void
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ar7100_device_register(device_t self, void *aux)
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{
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if (device_is_a(self, "com")) {
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prop_number_t pn =
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prop_number_create_unsigned_integer(atheros_get_bus_freq());
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KASSERT(pn != NULL);
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prop_dictionary_set(device_properties(self), "frequency", pn);
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prop_object_release(pn);
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}
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}
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static int
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ar7100_enable_device(const struct atheros_device *adv)
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{
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#if 0
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if (adv->adv_mask && ((adv->adv_mask & info->config) == 0)) {
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return -1;
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}
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#endif
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if (adv->adv_reset) {
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/* put device into reset */
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PUTRESETREG(AR7100_RESET_RESETCTL,
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GETRESETREG(AR7100_RESET_RESETCTL) | adv->adv_reset);
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delay(15000); /* XXX: tsleep? */
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/* take it out of reset */
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PUTRESETREG(AR7100_RESET_RESETCTL,
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GETRESETREG(AR7100_RESET_RESETCTL) & ~adv->adv_reset);
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delay(25);
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}
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if (adv->adv_enable) {
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panic("%s: %s: enable not supported!", __func__, adv->adv_name);
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#if 0
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PUTRESETREG(AR7100_RESET_ENABLE,
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GETRESETREG(AR7100_RESET_ENABLE) | adv->adv_enable);
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#endif
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}
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return 0;
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}
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static const struct atheros_device ar7100_devices[] = {
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{
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.adv_name = "com",
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.adv_addr = AR7100_UART_BASE,
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.adv_size = 0x1000,
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.adv_cirq = ARCHIP_CPU_IRQ_MISC,
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.adv_mirq = AR7100_MISC_IRQ_UART0,
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}, {
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.adv_name = "arpci",
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.adv_addr = AR7100_PCI_BASE,
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.adv_size = 0x2000,
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.adv_cirq = AR7100_CPU_IRQ_PCI,
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.adv_mirq = -1,
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.adv_reset = AR7100_RESETCTL_PCI_CORE_RESET,
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}, {
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.adv_name = "ohci",
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.adv_addr = AR7100_OHCI_BASE,
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.adv_size = 0x2000,
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.adv_cirq = ARCHIP_CPU_IRQ_USB,
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.adv_mirq = -1,
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}, {
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.adv_name = "ehci",
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.adv_addr = AR7100_EHCI_BASE,
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.adv_size = 0x2000,
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.adv_cirq = ARCHIP_CPU_IRQ_USB,
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.adv_mirq = -1,
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}, {
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.adv_name = "age",
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.adv_addr = AR7100_GMAC0_BASE,
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.adv_size = 0x2000,
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.adv_cirq = ARCHIP_CPU_IRQ_GMAC0,
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.adv_mirq = -1,
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}, {
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.adv_name = "age",
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.adv_addr = AR7100_GMAC1_BASE,
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.adv_size = 0x2000,
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.adv_cirq = ARCHIP_CPU_IRQ_GMAC1,
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.adv_mirq = -1,
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}, {
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.adv_name = NULL,
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}
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};
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const struct atheros_platformsw ar7100_platformsw = {
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.apsw_intrsw = &atheros_intrsw,
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.apsw_intr_init = ar7100_intr_init,
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.apsw_cpu_intrnames = ar7100_cpu_intrnames,
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.apsw_misc_intrnames = ar7100_misc_intrnames,
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.apsw_cpu_nintrs = __arraycount(ar7100_cpu_intrnames),
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.apsw_misc_nintrs = __arraycount(ar7100_misc_intrnames),
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.apsw_cpuirq_misc = ARCHIP_CPU_IRQ_MISC,
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.apsw_ipl_sr_map = &ar7100_ipl_sr_map,
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.apsw_revision_id_addr = ARCHIP_RESET_BASE + ARCHIP_RESET_REVISION,
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.apsw_uart0_base = AR7100_UART_BASE,
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.apsw_misc_intstat = ARCHIP_RESET_BASE + ARCHIP_RESET_MISC_INTSTAT,
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.apsw_misc_intmask = ARCHIP_RESET_BASE + ARCHIP_RESET_MISC_INTMASK,
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/*
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* CPU specific routines.
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*/
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.apsw_get_memsize = ar7100_get_memsize,
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.apsw_wdog_reload = ar7100_wdog_reload,
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.apsw_bus_init = ar7100_bus_init,
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.apsw_reset = ar7100_reset,
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.apsw_get_freqs = ar7100_get_freqs,
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.apsw_device_register = ar7100_device_register,
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.apsw_enable_device = ar7100_enable_device,
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.apsw_devices = ar7100_devices,
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};
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