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343 lines
8.6 KiB
C
343 lines
8.6 KiB
C
/* $NetBSD: arpci.c,v 1.5 2015/10/02 05:22:51 msaitoh Exp $ */
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/*-
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* Copyright (c) 2011 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: arpci.c,v 1.5 2015/10/02 05:22:51 msaitoh Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <dev/pci/pcivar.h>
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#include <mips/locore.h>
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#include <mips/atheros/include/arbusvar.h>
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#include <mips/atheros/include/ar9344reg.h>
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#define PCI_CMD_CFG_READ 0xa
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#define PCI_CMD_CFG_WRITE 0xb
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struct arpci_softc {
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device_t sc_dev;
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bus_dma_tag_t sc_dmat;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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struct mips_bus_space sc_memt;
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struct mips_pci_chipset sc_pc;
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bool sc_pcie;
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u_int sc_pba_flags;
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};
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static void arpci_bus_mem_init(bus_space_tag_t, void *);
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static void
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arpci_attach_hook(device_t parent, device_t self,
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struct pcibus_attach_args *pba)
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{
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}
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static int
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arpci_bus_maxdevs(void *v, int busno)
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{
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struct arpci_softc * const sc = v;
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if (busno == 0)
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return (sc->sc_pcie ? 1 : 22);
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return 32;
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}
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static pcitag_t
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arpci_make_tag(void *v, int bus, int dev, int func)
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{
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if (bus == 0 && dev == 0) {
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/*
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* Local access
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*/
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return (func << 8);
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}
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if (bus == 0 && dev < 21) {
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/*
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* Type 0 can only access 21 (32 - 11) devices starting at * device 0 (0 is needed for inbound transactions).
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* AD[11:32] encodes the idsel for the transaction
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* (only one bit can be set).
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* AD[8:11] contains function
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* AD[2:7] contains the register offset.
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* AD[0:1] must be zero.
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*/
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return (1 << (dev + 11)) | (func << 8);
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}
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/*
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* Type 1 Confugration Transaction.
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*/
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return (bus << 16) | (dev << 11) | (func << 8) | 1;
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}
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static void
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arpci_decompose_tag(void *v, pcitag_t tag, int *busp, int *devp, int *funcp)
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{
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if (tag & 1) {
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if (busp)
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*busp = (tag >> 16) & 255;
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if (devp)
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*devp = (tag >> 11) & 31;
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} else {
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if (busp)
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*busp = 0;
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if (devp) {
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if (tag & ~0x7ff) {
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*devp = ffs(tag >> 11) - 1;
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} else {
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*devp = 0;
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}
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}
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}
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if (funcp)
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*funcp = (tag >> 8) & 7;
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}
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static pcireg_t
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arpci_conf_read(void *v, pcitag_t tag, int reg)
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{
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struct arpci_softc * const sc = v;
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pcireg_t rv = 0xffffffff;
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if ((unsigned int)reg >= PCI_CONF_SIZE)
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return rv;
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if ((tag & 0x00ff0001) == 1) {
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KASSERT(((tag >> 11) & 31) > 20);
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/*
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* This was a type 0 transaction for a device > 20 which
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* we can't support.
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*/
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return rv;
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}
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tag |= reg & -4;
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#if 0
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR,
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bus_space_read_4(sc->sc_bst, sc->sc_bsh, AR7100_PCI_ERROR) & 3);
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#endif
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bus_space_handle_t addr = sc->sc_bsh;
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if ((tag & ~0x7fe) == 0) {
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_READ | tag);
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addr += AR7100_PCI_LCL_CFG_RDATA;
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printf("%s: tag %#lx: ", __func__, tag);
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} else {
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_CFG_ADDR, tag);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_CFG_CMD, PCI_CMD_CFG_READ);
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addr += AR7100_PCI_CFG_RDATA;
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printf("%s: AD[0:31] 0x%08lx: ", __func__, tag);
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}
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rv = kfetch_32((void *)addr, 0xffffffff);
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printf("%#x\n", rv);
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return rv;
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}
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static void
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arpci_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data)
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{
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struct arpci_softc * const sc = v;
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if ((unsigned int)reg >= PCI_CONF_SIZE)
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return;
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if ((tag & 0x00ff0001) == 1) {
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KASSERT(((tag >> 11) & 31) > 20);
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/*
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* This was a type 0 transaction for a device > 20 which
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* we can't support.
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*/
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return;
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}
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tag |= reg & -4;
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if ((tag & ~0x7fe) == 0) {
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_LCL_CFG_CMD, AR7100_PCI_LCL_CFG_CMD_WRITE | tag);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_LCL_CFG_WDATA, data);
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} else {
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_CFG_ADDR, tag);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_CFG_CMD, PCI_CMD_CFG_WRITE);
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bus_space_write_4(sc->sc_bst, sc->sc_bsh,
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AR7100_PCI_CFG_WDATA, data);
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}
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}
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static int
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arpci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
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{
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return EINVAL;
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}
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static const char *
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arpci_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len)
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{
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snprintf(buf, len, "fixme!");
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return buf;
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}
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static const struct evcnt *
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arpci_intr_evcnt(void *v, pci_intr_handle_t ih)
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{
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return NULL;
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}
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static void *
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arpci_intr_establish(void *v, pci_intr_handle_t ih,
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int ipl, int (*func)(void *), void *arg)
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{
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return NULL;
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}
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static void
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arpci_intr_disestablish(void *v, void *cookie)
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{
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}
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static void
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arpci_conf_interrupt(void *v, int bus, int dev, int func, int swiz, int *ilinep)
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{
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}
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static void
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arpci_chipset_init(struct arpci_softc *sc)
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{
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pci_chipset_tag_t pc = &sc->sc_pc;
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pc->pc_conf_v = sc;
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pc->pc_attach_hook = arpci_attach_hook;
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pc->pc_bus_maxdevs = arpci_bus_maxdevs;
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pc->pc_make_tag = arpci_make_tag;
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pc->pc_decompose_tag = arpci_decompose_tag;
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pc->pc_conf_read = arpci_conf_read;
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pc->pc_conf_write = arpci_conf_write;
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pc->pc_intr_v = sc;
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pc->pc_intr_map = arpci_intr_map;
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pc->pc_intr_string = arpci_intr_string;
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pc->pc_intr_evcnt = arpci_intr_evcnt;
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pc->pc_intr_establish = arpci_intr_establish;
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pc->pc_intr_disestablish = arpci_intr_disestablish;
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pc->pc_conf_interrupt = arpci_conf_interrupt;
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#ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
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//pc->pc_pciide_compat_intr_establish = arpci_pciide_compat_intr_establish;
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#endif
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}
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static int
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arpci_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct arbus_attach_args * const aa = aux;
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bus_space_handle_t bsh;
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if (strcmp(aa->aa_name, cf->cf_name) != 0)
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return 0;
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if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0, &bsh))
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return 0;
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bus_space_unmap(aa->aa_bst, bsh, aa->aa_size);
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return 1;
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}
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static void
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arpci_attach(device_t parent, device_t self, void *aux)
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{
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struct arbus_attach_args * const aa = aux;
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struct arpci_softc * const sc = device_private(self);
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sc->sc_dev = self;
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sc->sc_bst = aa->aa_bst;
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sc->sc_dmat = aa->aa_dmat;
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sc->sc_pcie = (strcmp(device_cfdata(self)->cf_name, "arpcie") == 0);
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if (bus_space_map(aa->aa_bst, aa->aa_addr, aa->aa_size, 0,
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&sc->sc_bsh)) {
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aprint_error(": failed to map registers\n");
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return;
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}
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aprint_normal(": PCI%s bus\n", (sc->sc_pcie ? "-Express x1" : ""));
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arpci_bus_mem_init(&sc->sc_memt, sc);
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arpci_chipset_init(sc);
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sc->sc_pba_flags |= PCI_FLAGS_MEM_OKAY;
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struct pcibus_attach_args pba;
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memset(&pba, 0, sizeof(pba));
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pba.pba_flags = sc->sc_pba_flags;
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if (pba.pba_flags & PCI_FLAGS_MEM_OKAY)
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pba.pba_memt = &sc->sc_memt;
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pba.pba_dmat = aa->aa_dmat;
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pba.pba_pc = &sc->sc_pc;
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pba.pba_bus = 0;
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config_found_ia(self, "pcibus", &pba, pcibusprint);
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}
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CFATTACH_DECL_NEW(arpci, sizeof(struct arpci_softc),
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arpci_match, arpci_attach, NULL, NULL);
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CFATTACH_DECL_NEW(arpcie, sizeof(struct arpci_softc),
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arpci_match, arpci_attach, NULL, NULL);
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#define CHIP arpci
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#define CHIP_LITTLE_ENDIAN /* defined */
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#define CHIP_MEM /* defined */
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#define CHIP_EXTENT /* defined */
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#define CHIP_EX_MALLOC_SAFE(v) true
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#define CHIP_W1_BUS_START(v) 0x10000000UL
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#define CHIP_W1_BUS_END(v) 0x16ffffffUL
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#define CHIP_W1_SYS_START(v) CHIP_W1_BUS_START(v)
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#define CHIP_W1_SYS_END(v) CHIP_W1_BUS_END(v)
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#include <mips/mips/bus_space_alignstride_chipdep.c>
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