mirror of
https://github.com/Stichting-MINIX-Research-Foundation/netbsd.git
synced 2025-09-09 23:27:35 -04:00
376 lines
14 KiB
C
376 lines
14 KiB
C
/* $NetBSD: octeon_fpareg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
|
|
|
|
/*
|
|
* Copyright (c) 2007 Internet Initiative Japan, Inc.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
* SUCH DAMAGE.
|
|
*/
|
|
|
|
/*
|
|
* FPA Registers
|
|
*/
|
|
|
|
#ifndef _OCTEON_FPAREG_H_
|
|
#define _OCTEON_FPAREG_H_
|
|
|
|
/* ---- register offsets */
|
|
|
|
#define FPA_INT_SUM 0x0001180028000040ULL
|
|
#define FPA_INT_ENB 0x0001180028000048ULL
|
|
#define FPA_CTL_STATUS 0x0001180028000050ULL
|
|
#define FPA_QUE0_AVAILABLE 0x0001180028000098ULL
|
|
#define FPA_QUE1_AVAILABLE 0x00011800280000a0ULL
|
|
#define FPA_QUE2_AVAILABLE 0x00011800280000a8ULL
|
|
#define FPA_QUE3_AVAILABLE 0x00011800280000b0ULL
|
|
#define FPA_QUE4_AVAILABLE 0x00011800280000b8ULL
|
|
#define FPA_QUE5_AVAILABLE 0x00011800280000c0ULL
|
|
#define FPA_QUE6_AVAILABLE 0x00011800280000c8ULL
|
|
#define FPA_QUE7_AVAILABLE 0x00011800280000d0ULL
|
|
#define FPA_WART_CTL 0x00011800280000d8ULL
|
|
#define FPA_WART_STATUS 0x00011800280000e0ULL
|
|
#define FPA_BIST_STATUS 0x00011800280000e8ULL
|
|
#define FPA_QUE0_PAGE_INDEX 0x00011800280000f0ULL
|
|
#define FPA_QUE1_PAGE_INDEX 0x00011800280000f8ULL
|
|
#define FPA_QUE2_PAGE_INDEX 0x0001180028000100ULL
|
|
#define FPA_QUE3_PAGE_INDEX 0x0001180028000108ULL
|
|
#define FPA_QUE4_PAGE_INDEX 0x0001180028000110ULL
|
|
#define FPA_QUE5_PAGE_INDEX 0x0001180028000118ULL
|
|
#define FPA_QUE6_PAGE_INDEX 0x0001180028000120ULL
|
|
#define FPA_QUE7_PAGE_INDEX 0x0001180028000128ULL
|
|
#define FPA_QUE_EXP 0x0001180028000130ULL
|
|
#define FPA_QUE_ACT 0x0001180028000138ULL
|
|
|
|
/* ---- register bit definitions */
|
|
|
|
#define FPA_INT_SUM_XXX_63_28 UINT64_C(0xfffffffff0000000)
|
|
#define FPA_INT_SUM_Q7_PERR UINT64_C(0x0000000008000000)
|
|
#define FPA_INT_SUM_Q7_COFF UINT64_C(0x0000000004000000)
|
|
#define FPA_INT_SUM_Q7_UND UINT64_C(0x0000000002000000)
|
|
#define FPA_INT_SUM_Q6_PERR UINT64_C(0x0000000001000000)
|
|
#define FPA_INT_SUM_Q6_COFF UINT64_C(0x0000000000800000)
|
|
#define FPA_INT_SUM_Q6_UND UINT64_C(0x0000000000400000)
|
|
#define FPA_INT_SUM_Q5_PERR UINT64_C(0x0000000000200000)
|
|
#define FPA_INT_SUM_Q5_COFF UINT64_C(0x0000000000100000)
|
|
#define FPA_INT_SUM_Q5_UND UINT64_C(0x0000000000080000)
|
|
#define FPA_INT_SUM_Q4_PERR UINT64_C(0x0000000000040000)
|
|
#define FPA_INT_SUM_Q4_COFF UINT64_C(0x0000000000020000)
|
|
#define FPA_INT_SUM_Q4_UND UINT64_C(0x0000000000010000)
|
|
#define FPA_INT_SUM_Q3_PERR UINT64_C(0x0000000000008000)
|
|
#define FPA_INT_SUM_Q3_COFF UINT64_C(0x0000000000004000)
|
|
#define FPA_INT_SUM_Q3_UND UINT64_C(0x0000000000002000)
|
|
#define FPA_INT_SUM_Q2_PERR UINT64_C(0x0000000000001000)
|
|
#define FPA_INT_SUM_Q2_COFF UINT64_C(0x0000000000000800)
|
|
#define FPA_INT_SUM_Q2_UND UINT64_C(0x0000000000000400)
|
|
#define FPA_INT_SUM_Q1_PERR UINT64_C(0x0000000000000200)
|
|
#define FPA_INT_SUM_Q1_COFF UINT64_C(0x0000000000000100)
|
|
#define FPA_INT_SUM_Q1_UND UINT64_C(0x0000000000000080)
|
|
#define FPA_INT_SUM_Q0_PERR UINT64_C(0x0000000000000040)
|
|
#define FPA_INT_SUM_Q0_COFF UINT64_C(0x0000000000000020)
|
|
#define FPA_INT_SUM_Q0_UND UINT64_C(0x0000000000000010)
|
|
#define FPA_INT_SUM_FED1_DBE UINT64_C(0x0000000000000008)
|
|
#define FPA_INT_SUM_FED1_SBE UINT64_C(0x0000000000000004)
|
|
#define FPA_INT_SUM_FED0_DBE UINT64_C(0x0000000000000002)
|
|
#define FPA_INT_SUM_FED0_SBE UINT64_C(0x0000000000000001)
|
|
|
|
#define FPA_INT_ENB_XXX_63_28 UINT64_C(0xfffffffff0000000)
|
|
#define FPA_INT_ENB_Q7_PERR UINT64_C(0x0000000008000000)
|
|
#define FPA_INT_ENB_Q7_COFF UINT64_C(0x0000000004000000)
|
|
#define FPA_INT_ENB_Q7_UND UINT64_C(0x0000000002000000)
|
|
#define FPA_INT_ENB_Q6_PERR UINT64_C(0x0000000001000000)
|
|
#define FPA_INT_ENB_Q6_COFF UINT64_C(0x0000000000800000)
|
|
#define FPA_INT_ENB_Q6_UND UINT64_C(0x0000000000400000)
|
|
#define FPA_INT_ENB_Q5_PERR UINT64_C(0x0000000000200000)
|
|
#define FPA_INT_ENB_Q5_COFF UINT64_C(0x0000000000100000)
|
|
#define FPA_INT_ENB_Q5_UND UINT64_C(0x0000000000080000)
|
|
#define FPA_INT_ENB_Q4_PERR UINT64_C(0x0000000000040000)
|
|
#define FPA_INT_ENB_Q4_COFF UINT64_C(0x0000000000020000)
|
|
#define FPA_INT_ENB_Q4_UND UINT64_C(0x0000000000010000)
|
|
#define FPA_INT_ENB_Q3_PERR UINT64_C(0x0000000000008000)
|
|
#define FPA_INT_ENB_Q3_COFF UINT64_C(0x0000000000004000)
|
|
#define FPA_INT_ENB_Q3_UND UINT64_C(0x0000000000002000)
|
|
#define FPA_INT_ENB_Q2_PERR UINT64_C(0x0000000000001000)
|
|
#define FPA_INT_ENB_Q2_COFF UINT64_C(0x0000000000000800)
|
|
#define FPA_INT_ENB_Q2_UND UINT64_C(0x0000000000000400)
|
|
#define FPA_INT_ENB_Q1_PERR UINT64_C(0x0000000000000200)
|
|
#define FPA_INT_ENB_Q1_COFF UINT64_C(0x0000000000000100)
|
|
#define FPA_INT_ENB_Q1_UND UINT64_C(0x0000000000000080)
|
|
#define FPA_INT_ENB_Q0_PERR UINT64_C(0x0000000000000040)
|
|
#define FPA_INT_ENB_Q0_COFF UINT64_C(0x0000000000000020)
|
|
#define FPA_INT_ENB_Q0_UND UINT64_C(0x0000000000000010)
|
|
#define FPA_INT_ENB_FED1_DBE UINT64_C(0x0000000000000008)
|
|
#define FPA_INT_ENB_FED1_SBE UINT64_C(0x0000000000000004)
|
|
#define FPA_INT_ENB_FED0_DBE UINT64_C(0x0000000000000002)
|
|
#define FPA_INT_ENB_FED0_SBE UINT64_C(0x0000000000000001)
|
|
|
|
#define FPA_CTL_STATUS_XXX_63_18 UINT64_C(0xfffffffffffc0000)
|
|
#define FPA_CTL_STATUS_RESET UINT64_C(0x0000000000020000)
|
|
#define FPA_CTL_STATUS_USE_LDT UINT64_C(0x0000000000010000)
|
|
#define FPA_CTL_STATUS_USE_STT UINT64_C(0x0000000000008000)
|
|
#define FPA_CTL_STATUS_ENB UINT64_C(0x0000000000004000)
|
|
#define FPA_CTL_STATUS_MEM1_ERR UINT64_C(0x0000000000003f80)
|
|
#define FPA_CTL_STATUS_MEM0_ERR UINT64_C(0x000000000000007f)
|
|
|
|
#define FPA_QUEX_AVAILABLE_XXX_63_29 UINT64_C(0xffffffffe0000000)
|
|
#define FPA_QUEX_AVAILABLE_QUE_SIZ UINT64_C(0x000000001fffffff)
|
|
|
|
#define FPA_WART_CTL_XXX_63_16 UINT64_C(0xffffffffffff0000)
|
|
#define FPA_WART_CTL_CTL UINT64_C(0x000000000000ffff)
|
|
|
|
#define FPA_WART_STATUS_XXX_63_32 UINT64_C(0xffffffff00000000)
|
|
#define FPA_WART_STATUS_STATUS UINT64_C(0x00000000ffffffff)
|
|
|
|
#define FPA_BIST_STATUS_XXX_63_5 UINT64_C(0xffffffffffffffe0)
|
|
#define FPA_BIST_STATUS_FRD UINT64_C(0x0000000000000010)
|
|
#define FPA_BIST_STATUS_FPF0 UINT64_C(0x0000000000000008)
|
|
#define FPA_BIST_STATUS_FPF1 UINT64_C(0x0000000000000004)
|
|
#define FPA_BIST_STATUS_FFR UINT64_C(0x0000000000000002)
|
|
#define FPA_BIST_STATUS_FDR UINT64_C(0x0000000000000001)
|
|
|
|
#define FPA_QUEX_PAGE_INDEX_XXX_63_25 UINT64_C(0xfffffffffe000000)
|
|
#define FPA_QUEX_PAGE_INDEX_PG_NUM UINT64_C(0x0000000001ffffff)
|
|
|
|
#define FPA_QUE_EXP_XXX_63_32 UINT64_C(0xffffffff00000000)
|
|
#define FPA_QUE_EXP_XXX_31_29 UINT64_C(0x00000000e0000000)
|
|
#define FPA_QUE_EXP_EXP_QUE UINT64_C(0x000000001c000000)
|
|
#define FPA_QUE_EXP_EXP_INDX UINT64_C(0x0000000003ffffff)
|
|
|
|
#define FPA_QUE_ACT_XXX_63_32 UINT64_C(0xffffffff00000000)
|
|
#define FPA_QUE_ACT_XXX_31_29 UINT64_C(0x00000000e0000000)
|
|
#define FPA_QUE_ACT_ACT_QUE UINT64_C(0x000000001c000000)
|
|
#define FPA_QUE_ACT_ACT_INDX UINT64_C(0x0000000003ffffff)
|
|
|
|
/* ---- snprintb(9) */
|
|
|
|
#define FPA_INT_SUM_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"b\x1b" "Q7_PERR\0" \
|
|
"b\x1a" "Q7_COFF\0" \
|
|
"b\x19" "Q7_UND\0" \
|
|
"b\x18" "Q6_PERR\0" \
|
|
"b\x17" "Q6_COFF\0" \
|
|
"b\x16" "Q6_UND\0" \
|
|
"b\x15" "Q5_PERR\0" \
|
|
"b\x14" "Q5_COFF\0" \
|
|
"b\x13" "Q5_UND\0" \
|
|
"b\x12" "Q4_PERR\0" \
|
|
"b\x11" "Q4_COFF\0" \
|
|
"b\x10" "Q4_UND\0" \
|
|
"b\x0f" "Q3_PERR\0" \
|
|
"b\x0e" "Q3_COFF\0" \
|
|
"b\x0d" "Q3_UND\0" \
|
|
"b\x0c" "Q2_PERR\0" \
|
|
"b\x0b" "Q2_COFF\0" \
|
|
"b\x0a" "Q2_UND\0" \
|
|
"b\x09" "Q1_PERR\0" \
|
|
"b\x08" "Q1_COFF\0" \
|
|
"b\x07" "Q1_UND\0" \
|
|
"b\x06" "Q0_PERR\0" \
|
|
"b\x05" "Q0_COFF\0" \
|
|
"b\x04" "Q0_UND\0" \
|
|
"b\x03" "FED1_DBE\0" \
|
|
"b\x02" "FED1_SBE\0" \
|
|
"b\x01" "FED0_DBE\0" \
|
|
"b\x00" "FED0_SBE\0"
|
|
|
|
#define FPA_INT_ENB_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"b\x1b" "Q7_PERR\0" \
|
|
"b\x1a" "Q7_COFF\0" \
|
|
"b\x19" "Q7_UND\0" \
|
|
"b\x18" "Q6_PERR\0" \
|
|
"b\x17" "Q6_COFF\0" \
|
|
"b\x16" "Q6_UND\0" \
|
|
"b\x15" "Q5_PERR\0" \
|
|
"b\x14" "Q5_COFF\0" \
|
|
"b\x13" "Q5_UND\0" \
|
|
"b\x12" "Q4_PERR\0" \
|
|
"b\x11" "Q4_COFF\0" \
|
|
"b\x10" "Q4_UND\0" \
|
|
"b\x0f" "Q3_PERR\0" \
|
|
"b\x0e" "Q3_COFF\0" \
|
|
"b\x0d" "Q3_UND\0" \
|
|
"b\x0c" "Q2_PERR\0" \
|
|
"b\x0b" "Q2_COFF\0" \
|
|
"b\x0a" "Q2_UND\0" \
|
|
"b\x09" "Q1_PERR\0" \
|
|
"b\x08" "Q1_COFF\0" \
|
|
"b\x07" "Q1_UND\0" \
|
|
"b\x06" "Q0_PERR\0" \
|
|
"b\x05" "Q0_COFF\0" \
|
|
"b\x04" "Q0_UND\0" \
|
|
"b\x03" "FED1_DBE\0" \
|
|
"b\x02" "FED1_SBE\0" \
|
|
"b\x01" "FED0_DBE\0" \
|
|
"b\x00" "FED0_SBE\0"
|
|
|
|
#define FPA_CTL_STATUS_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"b\x11" "RESET\0" \
|
|
"b\x10" "USE_LDT\0" \
|
|
"b\x0f" "USE_STT\0" \
|
|
"b\x0e" "ENB\0" \
|
|
"f\x07\x07" "MEM1_ERR\0" \
|
|
"f\x00\x07" "MEM0_ERR\0"
|
|
|
|
#define FPA_QUEX_AVAILABLE_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x00\x1d" "QUE_SIZ\0"
|
|
#define FPA_QUE0_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE1_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE2_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE3_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE4_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE5_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE6_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
#define FPA_QUE7_AVAILABLE_BITS FPA_QUEX_AVAILABLE_BITS
|
|
|
|
#define FPA_WART_CTL_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x00\x10" "CTL\0"
|
|
|
|
#define FPA_WART_STATUS_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x00\x20" "STATUS\0"
|
|
|
|
#define FPA_BIST_STATUS_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"b\x04" "FRD\0" \
|
|
"b\x03" "FPF0\0" \
|
|
"b\x02" "FPF1\0" \
|
|
"b\x01" "FFR\0" \
|
|
"b\x00" "FDR\0"
|
|
|
|
#define FPA_QUEX_PAGE_INDEX_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x00\x19" "PG_NUM\0"
|
|
#define FPA_QUE0_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE1_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE2_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE3_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE4_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE5_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE6_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
#define FPA_QUE7_PAGE_INDEX_BITS FPA_QUEX_PAGE_INDEX_BITS
|
|
|
|
#define FPA_QUE_EXP_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x1a\x03" "EXP_QUE\0" \
|
|
"f\x00\x1a" "EXP_INDX\0"
|
|
|
|
#define FPA_QUE_ACT_BITS \
|
|
"\177" /* new format */ \
|
|
"\020" /* hex display */ \
|
|
"\020" /* %016x format */ \
|
|
"f\x1a\x03" "ACT_QUE\0" \
|
|
"f\x00\x1a" "ACT_INDX\0"
|
|
|
|
/* ---- operations */
|
|
|
|
/*
|
|
* Free Pool Unit Operations
|
|
*/
|
|
|
|
#define FPA_MAJORDID 0x5 /* 0b00101 */
|
|
|
|
#define FPA_OPS_MAJORDID UINT64_C(0x0000f80000000000)
|
|
#define FPA_OPS_MAJORDID_SHIFT 43
|
|
#define FPA_OPS_SUBDID UINT64_C(0x0000070000000000)
|
|
#define FPA_OPS_SUBDID_SHIFT 40
|
|
#define FPA_OPS_XXX_39_0 UINT64_C(0x000000ffffffffff)
|
|
|
|
/* Load Operations */
|
|
|
|
#define FPA_OPS_LOAD_1 UINT64_C(0x0001000000000000)
|
|
#define FPA_OPS_LOAD_MAJORDID UINT64_C(0x0000f80000000000)
|
|
#define FPA_OPS_LOAD_SUBDID UINT64_C(0x0000070000000000)
|
|
#define FPA_OPS_LOAD_XXX_39_0 UINT64_C(0x000000ffffffffff)
|
|
|
|
/* IOBDMA Operations */
|
|
|
|
#define FPA_OPS_IOBDMA_SRCADDR UINT64_C(0xff00000000000000)
|
|
#define FPA_OPS_IOBDMA_LEN UINT64_C(0x00ff000000000000)
|
|
#define FPA_OPS_IOBDMA_LEN_SHIFT 48
|
|
#define FPA_OPS_IOBDMA_MAJORDID UINT64_C(0x0000f80000000000)
|
|
#define FPA_OPS_IOBDMA_SUBDIR UINT64_C(0x0000070000000000)
|
|
#define FPA_OPS_IOBDMA_XXX_39_0 UINT64_C(0x000000ffffffffff)
|
|
|
|
/* Store Operations */
|
|
|
|
#define FPA_OPS_STORE_1 UINT64_C(0x0001000000000000)
|
|
#define FPA_OPS_STORE_MAJORDID UINT64_C(0x0000f80000000000)
|
|
#define FPA_OPS_STORE_SUBDID UINT64_C(0x0000070000000000)
|
|
#define FPA_OPS_STORE_XXX_39_0 UINT64_C(0x000000ffffffffff)
|
|
|
|
#define FPA_OPS_STORE_DATA_XXX_63_9 UINT64_C(0xfffffffffffffe00)
|
|
#define FPA_OPS_STORE_DATA_DWBCOUNT UINT64_C(0x00000000000001ff)
|
|
|
|
/* ---- bus_space(9) */
|
|
|
|
#define FPA_BASE 0x0001180028000000ULL
|
|
#define FPA_SIZE 0x0200
|
|
|
|
#define FPA_INT_SUM_OFFSET 0x0040
|
|
#define FPA_INT_ENB_OFFSET 0x0048
|
|
#define FPA_CTL_STATUS_OFFSET 0x0050
|
|
#define FPA_QUE0_AVAILABLE_OFFSET 0x0098
|
|
#define FPA_QUE1_AVAILABLE_OFFSET 0x00a0
|
|
#define FPA_QUE2_AVAILABLE_OFFSET 0x00a8
|
|
#define FPA_QUE3_AVAILABLE_OFFSET 0x00b0
|
|
#define FPA_QUE4_AVAILABLE_OFFSET 0x00b8
|
|
#define FPA_QUE5_AVAILABLE_OFFSET 0x00c0
|
|
#define FPA_QUE6_AVAILABLE_OFFSET 0x00c8
|
|
#define FPA_QUE7_AVAILABLE_OFFSET 0x00d0
|
|
#define FPA_WART_CTL_OFFSET 0x00d8
|
|
#define FPA_WART_STATUS_OFFSET 0x00e0
|
|
#define FPA_BIST_STATUS_OFFSET 0x00e8
|
|
#define FPA_QUE0_PAGE_INDEX_OFFSET 0x00f0
|
|
#define FPA_QUE1_PAGE_INDEX_OFFSET 0x00f8
|
|
#define FPA_QUE2_PAGE_INDEX_OFFSET 0x0100
|
|
#define FPA_QUE3_PAGE_INDEX_OFFSET 0x0108
|
|
#define FPA_QUE4_PAGE_INDEX_OFFSET 0x0110
|
|
#define FPA_QUE5_PAGE_INDEX_OFFSET 0x0118
|
|
#define FPA_QUE6_PAGE_INDEX_OFFSET 0x0120
|
|
#define FPA_QUE7_PAGE_INDEX_OFFSET 0x0128
|
|
#define FPA_QUE_EXP_OFFSET 0x0130
|
|
#define FPA_QUE_ACT_OFFSET 0x0138
|
|
|
|
#endif /* _OCTEON_FPAREG_H_ */
|