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127 lines
4.8 KiB
C
127 lines
4.8 KiB
C
/* $NetBSD: octeon_gpioreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
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/*
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* Copyright (c) 2007 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* GPIO Registers
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*/
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#ifndef _OCTEON_GPIOREG_H_
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#define _OCTEON_GPIOREG_H_
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#define GPIO_BIT_CFG0 0x0001070000000800ULL
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#define GPIO_BIT_CFG1 0x0001070000000808ULL
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#define GPIO_BIT_CFG2 0x0001070000000810ULL
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#define GPIO_BIT_CFG3 0x0001070000000818ULL
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#define GPIO_BIT_CFG4 0x0001070000000820ULL
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#define GPIO_BIT_CFG5 0x0001070000000828ULL
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#define GPIO_BIT_CFG6 0x0001070000000830ULL
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#define GPIO_BIT_CFG7 0x0001070000000838ULL
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#define GPIO_BIT_CFG8 0x0001070000000840ULL
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#define GPIO_BIT_CFG9 0x0001070000000848ULL
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#define GPIO_BIT_CFG10 0x0001070000000850ULL
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#define GPIO_BIT_CFG11 0x0001070000000858ULL
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#define GPIO_BIT_CFG12 0x0001070000000860ULL
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#define GPIO_BIT_CFG13 0x0001070000000868ULL
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#define GPIO_BIT_CFG14 0x0001070000000870ULL
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#define GPIO_BIT_CFG15 0x0001070000000878ULL
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#define GPIO_RX_DAT 0x0001070000000880ULL
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#define GPIO_TX_SET 0x0001070000000888ULL
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#define GPIO_TX_CLR 0x0001070000000890ULL
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#define GPIO_INT_CLR 0x0001070000000898ULL
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#define GPIO_DBG_ENA 0x00010700000008a0ULL
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#define GPIO_BOOT_ENA 0x00010700000008a8ULL
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#define GPIO_XBIT_CFG16 0x0001070000000900ULL
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#define GPIO_XBIT_CFG17 0x0001070000000908ULL
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#define GPIO_XBIT_CFG18 0x0001070000000910ULL
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#define GPIO_XBIT_CFG19 0x0001070000000918ULL
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#define GPIO_XBIT_CFG20 0x0001070000000920ULL
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#define GPIO_XBIT_CFG21 0x0001070000000928ULL
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#define GPIO_XBIT_CFG22 0x0001070000000930ULL
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#define GPIO_XBIT_CFG23 0x0001070000000938ULL
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#define GPIO_BIT_CFG_XXX_63_12 UINT64_C(0xfffffffffffff000)
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#define GPIO_BIT_CFG_FIL_SEL UINT64_C(0x0000000000000f00)
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#define GPIO_BIT_CFG_FIL_CNT UINT64_C(0x00000000000000f0)
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#define GPIO_BIT_CFG_INT_TYPE UINT64_C(0x0000000000000008)
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#define GPIO_BIT_CFG_INT_EN UINT64_C(0x0000000000000004)
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#define GPIO_BIT_CFG_RX_XOR UINT64_C(0x0000000000000002)
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#define GPIO_BIT_CFG_TX_OE UINT64_C(0x0000000000000001)
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/* XXX */
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/* ---- snprintb */
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#define GPIO_BIT_CFG_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x08\x04" "FIL_SEL\0" \
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"f\x04\x04" "FIL_CNT\0" \
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"b\x03" "INT_TYPE\0" \
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"b\x02" "INT_EN\0" \
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"b\x01" "RX_XOR\0" \
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"b\x00" "TX_OE\0"
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/* ---- bus_space */
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#define GPIO_BASE 0x0001070000000800ULL
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#define GPIO_SIZE 0x0200
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#define GPIO_BIT_CFG0_OFFSET 0x0000
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#define GPIO_BIT_CFG1_OFFSET 0x0008
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#define GPIO_BIT_CFG2_OFFSET 0x0010
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#define GPIO_BIT_CFG3_OFFSET 0x0018
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#define GPIO_BIT_CFG4_OFFSET 0x0020
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#define GPIO_BIT_CFG5_OFFSET 0x0028
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#define GPIO_BIT_CFG6_OFFSET 0x0030
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#define GPIO_BIT_CFG7_OFFSET 0x0038
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#define GPIO_BIT_CFG8_OFFSET 0x0040
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#define GPIO_BIT_CFG9_OFFSET 0x0048
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#define GPIO_BIT_CFG10_OFFSET 0x0050
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#define GPIO_BIT_CFG11_OFFSET 0x0058
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#define GPIO_BIT_CFG12_OFFSET 0x0060
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#define GPIO_BIT_CFG13_OFFSET 0x0068
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#define GPIO_BIT_CFG14_OFFSET 0x0070
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#define GPIO_BIT_CFG15_OFFSET 0x0078
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#define GPIO_RX_DAT_OFFSET 0x0080
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#define GPIO_TX_SET_OFFSET 0x0088
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#define GPIO_TX_CLR_OFFSET 0x0090
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#define GPIO_INT_CLR_OFFSET 0x0098
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#define GPIO_DBG_ENA_OFFSET 0x00a0
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#define GPIO_BOOT_ENA_OFFSET 0x00a8
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#define GPIO_XBIT_CFG16_OFFSET 0x0100
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#define GPIO_XBIT_CFG17_OFFSET 0x0108
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#define GPIO_XBIT_CFG18_OFFSET 0x0110
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#define GPIO_XBIT_CFG19_OFFSET 0x0118
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#define GPIO_XBIT_CFG20_OFFSET 0x0120
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#define GPIO_XBIT_CFG21_OFFSET 0x0128
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#define GPIO_XBIT_CFG22_OFFSET 0x0130
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#define GPIO_XBIT_CFG23_OFFSET 0x0138
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#endif /* _OCTEON_GPIOREG_H_ */
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