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89 lines
3.3 KiB
C
89 lines
3.3 KiB
C
/* $NetBSD: octeon_smireg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
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/*
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* Copyright (c) 2007 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* SMI Registers
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*/
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#ifndef _OCTEON_SMIREG_H_
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#define _OCTEON_SMIREG_H_
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#define SMI_CMD 0x0001180000001800ULL
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#define SMI_WR_DAT 0x0001180000001808ULL
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#define SMI_RD_DAT 0x0001180000001810ULL
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#define SMI_CLK 0x0001180000001818ULL
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#define SMI_EN 0x0001180000001820ULL
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#define SMI_CMD_OFFSET 0x00ULL
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#define SMI_WR_DAT_OFFSET 0x08ULL
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#define SMI_RD_DAT_OFFSET 0x10ULL
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#define SMI_CLK_OFFSET 0x18ULL
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#define SMI_EN_OFFSET 0x20ULL
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#define SMI_BASE 0x0001180000001800ULL
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#define SMI_SIZE 0x028ULL
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/* SMI CMD */
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#define SMI_CMD_63_17 UINT64_C(0xfffffffffffe0000)
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#define SMI_CMD_PHY_OP UINT64_C(0x0000000000010000)
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#define SMI_CMD_15_13 UINT64_C(0x000000000000e000)
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#define SMI_CMD_PHY_ADR UINT64_C(0x0000000000001f00)
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#define SMI_CMD_PHY_ADR_SHIFT 8
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#define SMI_CMD_7_5 UINT64_C(0x00000000000000e0)
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#define SMI_CMD_REG_ADR UINT64_C(0x000000000000001f)
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#define SMI_CMD_REG_ADR_SHIFT 0
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/* SMI_WR_DAT */
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#define SMI_WR_DAT_63_18 UINT64_C(0xfffffffffffc0000)
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#define SMI_WR_DAT_PENDING UINT64_C(0x0000000000020000)
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#define SMI_WR_DAT_VAL UINT64_C(0x0000000000010000)
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#define SMI_WR_DAT_DAT UINT64_C(0x000000000000ffff)
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/* SMI_RD_DAT */
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#define SMI_RD_DAT_63_18 UINT64_C(0xfffffffffffc0000)
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#define SMI_RD_DAT_PENDING UINT64_C(0x0000000000020000)
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#define SMI_RD_DAT_VAL UINT64_C(0x0000000000010000)
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#define SMI_RD_DAT_DAT UINT64_C(0x000000000000ffff)
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/* SMI_CLK */
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#define SMI_CLK_63_21 UINT64_C(0xffffffffffe00000)
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#define SMI_CLK_SAMPLE_HI UINT64_C(0x00000000001f0000)
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#define SMI_CLK_15_14 UINT64_C(0x000000000000c000)
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#define SMI_CLK_CLK_IDLE UINT64_C(0x0000000000002000)
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#define SMI_CLK_PREAMBLE UINT64_C(0x0000000000001000)
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#define SMI_CLK_SAMPLE UINT64_C(0x0000000000000f00)
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#define SMI_CLK_PHASE UINT64_C(0x00000000000000ff)
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/* SMI_EN */
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#define SMI_EN_63_1 UINT64_C(0xfffffffffffffffe)
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#define SMI_EN_EN UINT64_C(0x0000000000000001)
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/* XXX */
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#endif /* _OCTEON_SMIREG_H_ */
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