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193 lines
6.5 KiB
C
193 lines
6.5 KiB
C
/* $NetBSD: octeon_timreg.h,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
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/*
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* Copyright (c) 2007 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Timer Registers
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*/
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#ifndef _OCTEON_TIMREG_H_
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#define _OCTEON_TIMREG_H_
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/* ---- register addresses */
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#define TIM_REG_FLAGS 0x0001180058000000ULL
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#define TIM_REG_READ_IDX 0x0001180058000008ULL
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#define TIM_REG_BIST_RESULT 0x0001180058000000ULL
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#define TIM_REG_ERROR 0x0001180058000088ULL
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#define TIM_REG_INT_MASK 0x0001180058000090ULL
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#define TIM_MEM_RING0 0x0001180058001000ULL
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#define TIM_MEM_RING1 0x0001180058001008ULL
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#define TIM_MEM_DEBUG0 0x0001180058001100ULL
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#define TIM_MEM_DEBUG1 0x0001180058001108ULL
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#define TIM_MEM_DEBUG2 0x0001180058001110ULL
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/* ---- register bits */
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#define TIM_REG_FLAGS_XXX_63_3 UINT64_C(0xfffffffffffffff8)
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#define TIM_REG_FLAGS_RESET UINT64_C(0x0000000000000004)
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#define TIM_REG_FLAGS_ENA_DWB UINT64_C(0x0000000000000002)
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#define TIM_REG_FLAGS_ENA_TIM UINT64_C(0x0000000000000001)
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#define TIM_REG_READ_IDX_XXX_63_16 UINT64_C(0xffffffffffff0000)
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#define TIM_REG_READ_IDX_INC UINT64_C(0x000000000000ff00)
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#define TIM_REG_READ_IDX_IDX UINT64_C(0x00000000000000ff)
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#define TIM_REG_BIST_RESULT_XXX_63_4 UINT64_C(0xfffffffffffffff0)
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#define TIM_REG_BIST_RESULT_STA UINT64_C(0x000000000000000c)
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#define TIM_REG_BIST_RESULT_NCB UINT64_C(0x0000000000000002)
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#define TIM_REG_BIST_RESULT_CTL UINT64_C(0x0000000000000001)
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#define TIM_REG_ERROR_XXX_63_16 UINT64_C(0xffffffffffff0000)
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#define TIM_REG_ERROR_MASK UINT64_C(0x000000000000ffff)
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#define TIM_REG_INT_XXX_63_16 UINT64_C(0xffffffffffff0000)
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#define TIM_REG_INT_MASK UINT64_C(0x000000000000ffff)
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#define TIM_MEM_RING0_XXX_63_55 UINT64_C(0xff80000000000000)
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#define TIM_MEM_RING0_BASE UINT64_C(0x007fffffff000000)
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#define TIM_MEM_RING0_BSIZE UINT64_C(0x0000000000fffff0)
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#define TIM_MEM_RING0_RID UINT64_C(0x000000000000000f)
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#define TIM_MEM_RING1_XXX_63_43 UINT64_C(0xfffff80000000000)
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#define TIM_MEM_RING1_ENA UINT64_C(0x0000040000000000)
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#define TIM_MEM_RING1_CPOOL UINT64_C(0x0000038000000000)
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#define TIM_MEM_RING1_CSIZE UINT64_C(0x0000007ffc000000)
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#define TIM_MEM_RING1_INTERVAL UINT64_C(0x0000000003fffff0)
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#define TIM_MEM_RING1_RID UINT64_C(0x000000000000000f)
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#define TIM_MEM_DEBUG0_XXX_63_48 UINT64_C(0xffff000000000000)
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#define TIM_MEM_DEBUG0_ENA UINT64_C(0x0000800000000000)
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#define TIM_MEM_DEBUG0_XXX_46 UINT64_C(0x0000400000000000)
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#define TIM_MEM_DEBUG0_COUNT UINT64_C(0x00003fffff000000)
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#define TIM_MEM_DEBUG0_XXX_23_22 UINT64_C(0x0000000000c00000)
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#define TIM_MEM_DEBUG0_INTERVAL UINT64_C(0x00000000003fffff)
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#define TIM_MEM_DEBUG1_BUCKET UINT64_C(0xfff8000000000000)
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#define TIM_MEM_DEBUG1_BASE UINT64_C(0x0007fffffff00000)
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#define TIM_MEM_DEBUG1_BSIZE UINT64_C(0x00000000000fffff)
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#define TIM_MEM_DEBUG2_XXX_63_32 UINT64_C(0xffffffff00000000)
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#define TIM_MEM_DEBUG2_XXX_31_24 UINT64_C(0x00000000ff000000)
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#define TIM_MEM_DEBUG2_CPOOL UINT64_C(0x0000000000e00000)
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#define TIM_MEM_DEBUG2_CSIZE UINT64_C(0x00000000001fff00)
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#define TIM_MEM_DEBUG2_XXX_7 UINT64_C(0x0000000000000080)
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#define TIM_MEM_DEBUG2_BUCKET UINT64_C(0x000000000000007f)
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/*
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* Timer Bucket Entry Structure
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*/
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struct tim_tbe {
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int64_t tim_tbe_first; /* first chunk (pointer) */
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uint32_t tim_tbe_nentries;
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uint32_t tim_tbe_remainder; /* chunk remainder */
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int64_t tim_tbe_current; /* current chunk (pointer) */
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uint64_t tim_tbe_pad;
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} __packed;
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/* ---- snprintb */
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#define TIM_REG_FLAGS_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"b\x02" "RESET\0" \
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"b\x01" "ENA_DWB\0" \
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"b\x00" "ENA_TIM\0"
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#define TIM_REG_READ_IDX_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x08\x08" "INC\0" \
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"f\x00\x08" "IDX\0"
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#define TIM_REG_BIST_RESULT_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x02\x02" "STA\0" \
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"b\x01" "NCB\0" \
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"b\x00" "CTL\0"
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#define TIM_REG_ERROR_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x00\x10" "MASK\0"
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#define TIM_REG_INT_MASK_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x00\x10" "TIM_REG_INT_MASK\0"
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#define TIM_MEM_RING0_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x18\x1f" "BASE\0" \
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"f\x04\x14" "BSIZE\0" \
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"f\x00\x04" "RID\0"
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#define TIM_MEM_RING1_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"b\x2a" "ENA\0" \
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"f\x27\x03" "CPOOL\0" \
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"f\x1a\x0d" "CSIZE\0" \
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"f\x04\x16" "INTERVAL\0" \
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"f\x00\x04" "RID\0"
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#define TIM_MEM_DEBUG0_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"b\x2f" "ENA\0" \
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"f\x18\x16" "COUNT\0" \
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"f\x00\x16" "INTERVAL\0"
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#define TIM_MEM_DEBUG1_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x33\x0d" "BUCKET\0" \
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"f\x14\x1f" "BASE\0" \
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"f\x00\x14" "BSIZE\0"
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#define TIM_MEM_DEBUG2_BITS \
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"\177" /* new format */ \
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"\020" /* hex display */ \
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"\020" /* %016x format */ \
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"f\x15\x03" "CPOOL\0" \
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"f\x08\x0d" "CSIZE\0" \
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"f\x00\x07" "BUCKET\0"
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#endif /* _OCTEON_TIMREG_H_ */
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