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538 lines
12 KiB
C
538 lines
12 KiB
C
/* $NetBSD: octeon_twsi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $ */
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/*
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* Copyright (c) 2007 Internet Initiative Japan, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#undef TWSIDEBUG
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#undef TWSITEST
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: octeon_twsi.c,v 1.1 2015/04/29 08:32:01 hikaru Exp $");
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#include "opt_octeon.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/types.h>
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#include <sys/device.h>
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#include <sys/lock.h>
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#include <sys/bus.h>
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#include <dev/i2c/i2cvar.h>
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#include <mips/cavium/include/iobusvar.h>
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#include <mips/cavium/dev/octeon_twsireg.h>
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#ifdef TWSIDEBUG
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#define DPRINTF(x) printf x
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#else
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#define DPRINTF(x)
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#endif
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struct octeon_twsi_reg;
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struct octeon_twsi_softc {
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device_t sc_dev;
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bus_space_tag_t sc_regt;
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bus_space_handle_t sc_regh;
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void *sc_ih;
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struct i2c_controller sc_i2c;
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struct lock sc_lock;
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/* ... */
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};
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/* Auto-configuration */
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static int octeon_twsi_match(device_t, struct cfdata *,
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void *);
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static void octeon_twsi_attach(device_t, device_t,
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void *);
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/* High-Level Controller Master */
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#ifdef notyet
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static uint8_t octeon_twsi_hlcm_read_1(struct octeon_twsi_softc *,
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...)
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static uint64_t octeon_twsi_hlcm_read_4(struct octeon_twsi_softc *,
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...)
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static void octeon_twsi_hlcm_read(struct octeon_twsi_softc *,
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...)
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static void octeon_twsi_hlcm_write_1(struct octeon_twsi_softc *,
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...)
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static void octeon_twsi_hlcm_write_4(struct octeon_twsi_softc *,
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...)
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static void octeon_twsi_hlcm_write(struct octeon_twsi_softc *,
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...)
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#endif
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/* High-Level Controller Slave */
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/* XXX */
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/* Control Register */
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#ifdef notyet
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#define _CONTROL_READ(sc, reg) \
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octeon_twsi_control_read((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg)
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#define _CONTROL_WRITE(sc, reg, value) \
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octeon_twsi_control_write((sc), MIO_TWS_SW_TWSI_EOP_IA_##reg, value)
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static uint8_t octeon_twsi_control_read(struct octeon_twsi_softc *sc,
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uint64_t);
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static void octeon_twsi_control_write(struct octeon_twsi_softc *sc,
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uint64_t, uint8_t);
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#endif
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/* Register accessors */
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static inline uint64_t octeon_twsi_reg_rd(struct octeon_twsi_softc *, int);
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static inline void octeon_twsi_reg_wr(struct octeon_twsi_softc *, int,
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uint64_t);
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#ifdef TWSIDEBUG
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static inline void octeon_twsi_reg_dump(struct octeon_twsi_softc *, int);
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#endif
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/* Test functions */
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#ifdef TWSIDEBUG
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static void octeon_twsi_test(struct octeon_twsi_softc *);
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#endif
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/* Debug functions */
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#ifdef TWSIDEBUG
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static inline void octeon_twsi_debug_reg_dump(struct octeon_twsi_softc *,
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int);
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static void octeon_twsi_debug_dumpregs(struct octeon_twsi_softc *);
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static void octeon_twsi_debug_dumpreg(struct octeon_twsi_softc *,
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const struct octeon_twsi_reg *);
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* Auto-configuration
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*/
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CFATTACH_DECL_NEW(octeon_twsi, sizeof(struct octeon_twsi_softc),
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octeon_twsi_match, octeon_twsi_attach, NULL, NULL);
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static int
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octeon_twsi_match(device_t parent, struct cfdata *cf, void *aux)
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{
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struct iobus_attach_args *aa = aux;
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if (strcmp(cf->cf_name, aa->aa_name) != 0)
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return 0;
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return 1;
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}
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static void
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octeon_twsi_attach(device_t parent, device_t self, void *aux)
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{
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struct octeon_twsi_softc *sc = device_private(self);
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struct iobus_attach_args *aa = aux;
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int status;
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sc->sc_dev = self;
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sc->sc_regt = aa->aa_bust;
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status = bus_space_map(sc->sc_regt, MIO_TWS_BASE_0, MIO_TWS_SIZE, 0,
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&sc->sc_regh);
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if (status != 0)
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panic(": can't map register");
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aprint_normal("\n");
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#ifdef TWSITEST
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octeon_twsi_test(sc);
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#endif
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}
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/* -------------------------------------------------------------------------- */
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/*
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* Initialization, basic operations
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*/
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#ifdef notyet
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static void
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octeon_twsi_wait(struct octeon_twsi_softc *sc)
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{
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}
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static void
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octeon_twsi_intr(struct octeon_twsi_softc *sc)
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{
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}
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static void
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octeon_twsi_lock(struct octeon_twsi_softc *sc)
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{
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}
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static void
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octeon_twsi_unlock(struct octeon_twsi_softc *sc)
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{
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* High-Level Controller as a Master
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*/
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#ifdef notyet
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#define _BUFTOLE32(buf) \
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((buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | (buf[3] << 0))
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#define _LE32TOBUF(buf, x) \
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do { \
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buf[0] = (char)((x) >> 24); \
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buf[1] = (char)((x) >> 16); \
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buf[2] = (char)((x) >> 8); \
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buf[3] = (char)((x) >> 0); \
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} while (0)
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static void
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octeon_twsi_hlcm_read(struct octeon_twsi_softc *sc, int addr, char *buf,
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size_t len)
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{
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uint64_t cmd;
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size_t resid;
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octeon_twsi_lock(sc);
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#ifdef notyet
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octeon_twsi_hlcm_setup(sc);
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resid = len;
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while (resid > 4) {
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cmd = MIO_TWS_SW_TWSI_OP_FOUR | MIO_TWS_SW_TWSI_R
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT);
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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cmd = octeon_twsi_reg_rd(sc);
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_LE32TOBUF(&buf[len - 1 - resid], (uint32_t)cmd);
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resid -= 4;
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}
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while (resid > 0) {
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cmd = MIO_TWS_SW_TWSI_OP_ONE | MIO_TWS_SW_TWSI_R
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT);
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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cmd = octeon_twsi_reg_rd(sc);
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buf[len - 1 - resid] = (uint8_t)cmd;
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resid--;
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}
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#endif
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octeon_twsi_unlock(sc);
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}
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static void
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octeon_twsi_hlcm_write(struct octeon_twsi_softc *sc, int addr, char *buf,
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size_t len)
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{
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uint64_t cmd;
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size_t resid;
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octeon_twsi_lock(sc);
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#ifdef notyet
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octeon_twsi_hlcm_setup(sc);
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resid = len;
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while (resid > 4) {
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cmd = MIO_TWS_SW_TWSI_OP_FOUR
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT)
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| _BUFTOLE32(&buf[len - 1 - resid]);
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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resid -= 4;
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}
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while (resid > 0) {
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cmd = MIO_TWS_SW_TWSI_OP_ONE
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT)
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| buf[len - 1 - resid];
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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resid--;
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}
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/* MIO_TWS_SW_TWSI:V must be zero */
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/* check error */
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if (MIO_TWS_SW_TWSI:R == 0) {
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code = MIO_TWS_SW_TWSI:D;
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}
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#endif
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octeon_twsi_unlock(sc);
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}
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static void
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octeon_twsi_hlcm_setup(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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_CONTROL_WR(sc, TWSI_CTL, TWSI_CTL_CE | TWSI_CTL_ENAB | TWSI_AAK);
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}
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static uint8_t
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octeon_twsi_hlcm_read_1(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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return 0;
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}
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static uint64_t
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octeon_twsi_hlcm_read_4(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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return 0;
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}
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static void
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octeon_twsi_hlcm_write_1(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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}
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static void
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octeon_twsi_hlcm_write_4(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* High-Level Controller as a Slave
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*/
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#ifdef notyet
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static void
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octeon_twsi_hlcs_setup(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* TWSI Control Register operations
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*/
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#ifdef notyet
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static uint8_t
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octeon_twsi_control_read(struct octeon_twsi_softc *sc, uint64_t eop_ia)
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{
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uint64_t cmd;
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cmd = MIO_TWS_SW_TWSI_OP_EXTEND
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT)
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| eop_ia;
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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return (uint8_t)octeon_twsi_reg_rd(sc, MIO_TWS_SW_TWSI_OFFSET);
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}
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static void
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octeon_twsi_control_write(struct octeon_twsi_softc *sc, uint64_t eop_ia,
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char *buf, size_t len)
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{
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uint64_t cmd;
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cmd = MIO_TWS_SW_TWSI_OP_EXTEND
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| (addr << MIO_TWS_SW_TWSI_A_SHIFT)
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| eop_ia
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| _BUFTOLE32(&buf[len - 1 - resid]);
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, cmd);
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octeon_twsi_wait(sc);
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* Send / receive operations
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*/
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/* Send (== software to TWSI) */
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#ifdef notyet
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static void
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octeon_twsi_send(struct octeon_twsi_softc *sc, ...)
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{
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, ...);
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}
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/* Receive (== TWSI to software) */
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static void
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octeon_twsi_recv(struct octeon_twsi_softc *sc, ...)
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{
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/* XXX */
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octeon_twsi_reg_wr(sc, MIO_TWS_SW_TWSI_OFFSET, ...);
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octeon_twsi_wait(sc, MIO_TWS_SW_TWSI_OFFSET, ...);
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octeon_twsi_reg_rd(sc, MIO_TWS_SW_TWSI_OFFSET, ...);
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* Register accessors
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*/
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static inline uint64_t
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octeon_twsi_reg_rd(struct octeon_twsi_softc *sc, int offset)
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{
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return bus_space_read_8(sc->sc_regt, sc->sc_regh, offset);
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}
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static inline void
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octeon_twsi_reg_wr(struct octeon_twsi_softc *sc, int offset, uint64_t value)
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{
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bus_space_write_8(sc->sc_regt, sc->sc_regh, offset, value);
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}
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#ifdef TWSIDEBUG
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void
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octeon_twsi_reg_dump(struct octeon_twsi_softc *sc, int offset)
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{
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octeon_twsi_debug_reg_dump(sc, offset);
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}
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#endif
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/* -------------------------------------------------------------------------- */
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/*
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* Test functions
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*/
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#ifdef TWSITEST
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void
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octeon_twsi_test(struct octeon_twsi_softc *sc)
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{
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octeon_twsi_debug_dumpregs(sc);
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}
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#endif
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/* -------------------------------------------------------------------------- */
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#ifdef TWSIDEBUG
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/*
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* Debug functions
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*
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* octeon_twsi_debug_reg_dump
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* octeon_twsi_debug_dumpregs
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* octeon_twsi_debug_dumpreg
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*/
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struct octeon_twsi_reg {
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const char *name;
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int offset;
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const char *format;
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};
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static const struct octeon_twsi_reg octeon_twsi_regs[] = {
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#define _ENTRY(x) { #x, x##_OFFSET, x##_BITS }
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_ENTRY(MIO_TWS_SW_TWSI),
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_ENTRY(MIO_TWS_TWSI_SW),
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_ENTRY(MIO_TWS_INT),
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_ENTRY(MIO_TWS_SW_TWSI_EXT)
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#undef _ENTRY
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};
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void
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octeon_twsi_debug_reg_dump(struct octeon_twsi_softc *sc, int offset)
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{
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int i;
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const struct octeon_twsi_reg *reg;
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reg = NULL;
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for (i = 0; i < (int)__arraycount(octeon_twsi_regs); i++)
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if (octeon_twsi_regs[i].offset == offset) {
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reg = &octeon_twsi_regs[i];
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break;
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}
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KASSERT(reg != NULL);
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octeon_twsi_debug_dumpreg(sc, reg);
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}
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void
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octeon_twsi_debug_dumpregs(struct octeon_twsi_softc *sc)
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{
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int i;
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for (i = 0; i < (int)__arraycount(octeon_twsi_regs); i++)
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octeon_twsi_debug_dumpreg(sc, &octeon_twsi_regs[i]);
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}
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void
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octeon_twsi_debug_dumpreg(struct octeon_twsi_softc *sc,
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const struct octeon_twsi_reg *reg)
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{
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uint64_t value;
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char buf[256];
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value = octeon_twsi_reg_rd(sc, reg->offset);
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snprintb(buf, sizeof(buf), reg->format, value);
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printf("\t%-24s: %s\n", reg->name, buf);
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}
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#endif
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