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57 lines
1.5 KiB
C
57 lines
1.5 KiB
C
/* $NetBSD: cache_octeon.h,v 1.1 2015/04/29 08:32:00 hikaru Exp $ */
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#define CACHE_OCTEON_I 0
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#define CACHE_OCTEON_D 1
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#define CACHEOP_OCTEON_INV_ALL (0 << 2) /* I, D */
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#define CACHEOP_OCTEON_INDEX_LOAD_TAG (1 << 2) /* I, D */
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#define CACHEOP_OCTEON_BITMAP_STORE (3 << 2) /* I */
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#define CACHEOP_OCTEON_VIRTUAL_TAG_INV (4 << 2) /* D */
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#if !defined(_LOCORE)
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/*
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* cache_octeon_invalidate:
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*
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* Invalidate all cahce blocks.
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* Argument "op" must be CACHE_OCTEON_I or CACHE_OCTEON_D.
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* In Octeon specification, invalidate instruction works
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* all cache blocks.
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*/
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#define cache_octeon_invalidate(op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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"cache %0, 0($0) \n\t" \
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".set reorder" \
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: \
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: "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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/*
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* cache_octeon_op_line:
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*
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* Perform the specified cache operation on a single line.
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*/
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#define cache_op_octeon_line(va, op) \
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do { \
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__asm __volatile( \
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".set noreorder \n\t" \
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"cache %1, 0(%0) \n\t" \
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".set reorder" \
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: \
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: "r" (va), "i" (op) \
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: "memory"); \
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} while (/*CONSTCOND*/0)
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void octeon_icache_sync_all(void);
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void octeon_icache_sync_range(vaddr_t va, vsize_t size);
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void octeon_icache_sync_range_index(vaddr_t va, vsize_t size);
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void octeon_pdcache_inv_all(void);
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void octeon_pdcache_inv_range(vaddr_t va, vsize_t size);
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void octeon_pdcache_inv_range_index(vaddr_t va, vsize_t size);
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void octeon_pdcache_wb_range(vaddr_t va, vsize_t size);
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#endif /* !_LOCORE */
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