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634 lines
18 KiB
C
634 lines
18 KiB
C
/* $NetBSD: locore.h,v 1.99 2015/06/09 15:01:05 matt Exp $ */
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/*
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* This file should not be included by MI code!!!
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*/
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/*
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* Copyright 1996 The Board of Trustees of The Leland Stanford
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* Junior University. All Rights Reserved.
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*
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* Permission to use, copy, modify, and distribute this
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* software and its documentation for any purpose and without
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* fee is hereby granted, provided that the above copyright
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* notice appear in all copies. Stanford University
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* makes no representations about the suitability of this
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* software for any purpose. It is provided "as is" without
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* express or implied warranty.
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*/
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/*
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* Jump table for MIPS CPU locore functions that are implemented
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* differently on different generations, or instruction-level
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* architecture (ISA) level, the Mips family.
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*
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* We currently provide support for MIPS I and MIPS III.
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*/
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#ifndef _MIPS_LOCORE_H
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#define _MIPS_LOCORE_H
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#if !defined(_LKM) && defined(_KERNEL_OPT)
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#include "opt_cputype.h"
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#endif
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#include <mips/mutex.h>
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#include <mips/cpuregs.h>
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#include <mips/reg.h>
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struct tlbmask;
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struct trapframe;
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void trap(uint32_t, uint32_t, vaddr_t, vaddr_t, struct trapframe *);
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void ast(void);
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void mips_fpu_trap(vaddr_t, struct trapframe *);
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void mips_fpu_intr(vaddr_t, struct trapframe *);
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vaddr_t mips_emul_branch(struct trapframe *, vaddr_t, uint32_t, bool);
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void mips_emul_inst(uint32_t, uint32_t, vaddr_t, struct trapframe *);
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void mips_emul_fp(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_branchdelayslot(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lwc0(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_swc0(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_special(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_special3(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lwc1(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_swc1(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_ldc1(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_sdc1(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lb(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lbu(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lh(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lhu(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lw(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lwl(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_lwr(uint32_t, struct trapframe *, uint32_t);
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#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
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void mips_emul_lwu(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_ld(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_ldl(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_ldr(uint32_t, struct trapframe *, uint32_t);
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#endif
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void mips_emul_sb(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_sh(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_sw(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_swl(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_swr(uint32_t, struct trapframe *, uint32_t);
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#if defined(__mips_n32) || defined(__mips_n64) || defined(__mips_o64)
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void mips_emul_sd(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_sdl(uint32_t, struct trapframe *, uint32_t);
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void mips_emul_sdr(uint32_t, struct trapframe *, uint32_t);
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#endif
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uint32_t mips_cp0_cause_read(void);
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void mips_cp0_cause_write(uint32_t);
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uint32_t mips_cp0_status_read(void);
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void mips_cp0_status_write(uint32_t);
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void softint_process(uint32_t);
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void softint_fast_dispatch(struct lwp *, int);
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/*
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* Convert an address to an offset used in a MIPS jump instruction. The offset
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* contains the low 28 bits (allowing a jump to anywhere within the same 256MB
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* segment of address space) of the address but since mips instructions are
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* always on a 4 byte boundary the low 2 bits are always zero so the 28 bits
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* get shifted right by 2 bits leaving us with a 26 bit result. To make the
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* offset, we shift left to clear the upper four bits and then right by 6.
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*/
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#define fixup_addr2offset(x) ((((uint32_t)(uintptr_t)(x)) << 4) >> 6)
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typedef bool (*mips_fixup_callback_t)(int32_t, uint32_t [2], void *);
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struct mips_jump_fixup_info {
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uint32_t jfi_stub;
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uint32_t jfi_real;
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};
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void fixup_splcalls(void); /* splstubs.c */
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bool mips_fixup_exceptions(mips_fixup_callback_t, void *);
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bool mips_fixup_zero_relative(int32_t, uint32_t [2], void *);
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intptr_t
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mips_fixup_addr(const uint32_t *);
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void mips_fixup_stubs(uint32_t *, uint32_t *);
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/*
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* Define these stubs...
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*/
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void mips_cpu_switch_resume(struct lwp *);
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void tlb_set_asid(uint32_t);
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void tlb_invalidate_all(void);
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void tlb_invalidate_globals(void);
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void tlb_invalidate_asids(uint32_t, uint32_t);
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void tlb_invalidate_addr(vaddr_t);
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u_int tlb_record_asids(u_long *, uint32_t);
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int tlb_update(vaddr_t, uint32_t);
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void tlb_enter(size_t, vaddr_t, uint32_t);
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void tlb_read_indexed(size_t, struct tlbmask *);
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void tlb_write_indexed(size_t, const struct tlbmask *);
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void wbflush(void);
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#ifdef MIPS1
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void mips1_tlb_invalidate_all(void);
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uint32_t tx3900_cp0_config_read(void);
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#endif
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#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
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uint32_t mips3_cp0_compare_read(void);
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void mips3_cp0_compare_write(uint32_t);
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uint32_t mips3_cp0_config_read(void);
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void mips3_cp0_config_write(uint32_t);
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#if (MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0
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uint32_t mipsNN_cp0_config1_read(void);
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void mipsNN_cp0_config1_write(uint32_t);
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uint32_t mipsNN_cp0_config2_read(void);
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uint32_t mipsNN_cp0_config3_read(void);
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intptr_t mipsNN_cp0_watchlo_read(u_int);
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void mipsNN_cp0_watchlo_write(u_int, intptr_t);
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uint32_t mipsNN_cp0_watchhi_read(u_int);
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void mipsNN_cp0_watchhi_write(u_int, uint32_t);
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int32_t mipsNN_cp0_ebase_read(void);
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void mipsNN_cp0_ebase_write(int32_t);
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#if (MIPS32R2 + MIPS64R2) > 0
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void mipsNN_cp0_hwrena_write(uint32_t);
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void mipsNN_cp0_userlocal_write(void *);
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#endif
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#endif
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uint32_t mips3_cp0_count_read(void);
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void mips3_cp0_count_write(uint32_t);
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uint32_t mips3_cp0_wired_read(void);
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void mips3_cp0_wired_write(uint32_t);
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void mips3_cp0_pg_mask_write(uint32_t);
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#if defined(__GNUC__) && !defined(__mips_o32)
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static inline uint64_t
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mips3_ld(const volatile uint64_t *va)
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{
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uint64_t rv;
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write(sr & ~MIPS_SR_INT_IE);
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__asm volatile(
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"ld %M0,0(%1) \n\t"
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"dsll32 %L0,%M0,0 \n\t"
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"dsra32 %M0,%M0,0 \n\t" /* high word */
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"dsra32 %L0,%L0,0 \n\t" /* low word */
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"ld %0,0(%1) \n\t"
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".set pop"
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: "=d"(rv)
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: "r"(va));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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rv = *va;
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#else
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__asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
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#endif
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return rv;
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}
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static inline void
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mips3_sd(volatile uint64_t *va, uint64_t v)
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{
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write(sr & ~MIPS_SR_INT_IE);
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__asm volatile(
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M0,%M0,0 \n\t"
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"dsll32 %L0,%L0,0 \n\t"
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"dsrl32 %L0,%L0,0 \n\t"
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"or %0,%L0,%M0 \n\t"
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"sd %0,0(%1) \n\t"
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".set pop"
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: "=d"(v) : "0"(v), "r"(va));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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*va = v;
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#else
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__asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
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#endif
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}
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#else
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uint64_t mips3_ld(volatile uint64_t *va);
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void mips3_sd(volatile uint64_t *, uint64_t);
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#endif /* __GNUC__ */
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#endif /* (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) > 0 */
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#if (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0
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static __inline uint32_t mips3_lw_a64(uint64_t addr) __unused;
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static __inline void mips3_sw_a64(uint64_t addr, uint32_t val) __unused;
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static __inline uint32_t
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mips3_lw_a64(uint64_t addr)
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{
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uint32_t rv;
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile (
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M1,%M1,0 \n\t"
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"dsll32 %L1,%L1,0 \n\t"
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"dsrl32 %L1,%L1,0 \n\t"
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"or %1,%M1,%L1 \n\t"
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"lw %0, 0(%1) \n\t"
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".set pop"
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: "=r"(rv), "=d"(addr)
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: "1"(addr)
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);
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mips_cp0_status_write(sr);
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#elif defined(__mips_n32)
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uint32_t sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile("lw %0, 0(%1)" : "=r"(rv) : "d"(addr));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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rv = *(const uint32_t *)addr;
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#else
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#error unknown ABI
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#endif
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return (rv);
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}
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static __inline void
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mips3_sw_a64(uint64_t addr, uint32_t val)
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{
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#if defined(__mips_o32)
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uint32_t sr;
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sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile (
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".set push \n\t"
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".set mips3 \n\t"
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".set noreorder \n\t"
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".set noat \n\t"
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"dsll32 %M0,%M0,0 \n\t"
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"dsll32 %L0,%L0,0 \n\t"
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"dsrl32 %L0,%L0,0 \n\t"
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"or %0,%M0,%L0 \n\t"
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"sw %1, 0(%0) \n\t"
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".set pop"
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: "=d"(addr): "r"(val), "0"(addr)
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);
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mips_cp0_status_write(sr);
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#elif defined(__mips_n32)
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uint32_t sr = mips_cp0_status_read();
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mips_cp0_status_write((sr & ~MIPS_SR_INT_IE) | MIPS3_SR_KX);
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__asm volatile("sw %1, 0(%0)" :: "d"(addr), "r"(val));
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mips_cp0_status_write(sr);
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#elif defined(_LP64)
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*(uint32_t *)addr = val;
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#else
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#error unknown ABI
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#endif
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}
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#endif /* (MIPS3 + MIPS4 + MIPS64 + MIPS64R2) > 0 */
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#if (MIPS64 + MIPS64R2) > 0 && !defined(__mips_o32)
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/* 64-bits address space accessor for n32, n64 ABI */
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static __inline uint64_t mips64_ld_a64(uint64_t addr) __unused;
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static __inline void mips64_sd_a64(uint64_t addr, uint64_t val) __unused;
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static __inline uint64_t
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mips64_ld_a64(uint64_t addr)
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{
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uint64_t rv;
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#if defined(__mips_n32)
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__asm volatile("ld %0, 0(%1)" : "=r"(rv) : "d"(addr));
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#elif defined(_LP64)
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rv = *(volatile uint64_t *)addr;
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#else
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#error unknown ABI
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#endif
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return (rv);
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}
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static __inline void
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mips64_sd_a64(uint64_t addr, uint64_t val)
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{
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#if defined(__mips_n32)
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__asm volatile("sd %1, 0(%0)" :: "d"(addr), "r"(val));
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#elif defined(_LP64)
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*(volatile uint64_t *)addr = val;
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#else
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#error unknown ABI
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#endif
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}
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#endif /* (MIPS64 + MIPS64R2) > 0 */
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/*
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* A vector with an entry for each mips-ISA-level dependent
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* locore function, and macros which jump through it.
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*/
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typedef struct {
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void (*ljv_cpu_switch_resume)(struct lwp *);
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intptr_t ljv_lwp_trampoline;
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void (*ljv_wbflush)(void);
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void (*ljv_tlb_set_asid)(uint32_t pid);
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void (*ljv_tlb_invalidate_asids)(uint32_t, uint32_t);
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void (*ljv_tlb_invalidate_addr)(vaddr_t);
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void (*ljv_tlb_invalidate_globals)(void);
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void (*ljv_tlb_invalidate_all)(void);
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u_int (*ljv_tlb_record_asids)(u_long *, uint32_t);
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int (*ljv_tlb_update)(vaddr_t, uint32_t);
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void (*ljv_tlb_enter)(size_t, vaddr_t, uint32_t);
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void (*ljv_tlb_read_indexed)(size_t, struct tlbmask *);
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void (*ljv_tlb_write_indexed)(size_t, const struct tlbmask *);
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} mips_locore_jumpvec_t;
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typedef struct {
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u_int (*lav_atomic_cas_uint)(volatile u_int *, u_int, u_int);
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u_long (*lav_atomic_cas_ulong)(volatile u_long *, u_long, u_long);
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int (*lav_ucas_uint)(volatile u_int *, u_int, u_int, u_int *);
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int (*lav_ucas_ulong)(volatile u_long *, u_long, u_long, u_long *);
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void (*lav_mutex_enter)(kmutex_t *);
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void (*lav_mutex_exit)(kmutex_t *);
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void (*lav_mutex_spin_enter)(kmutex_t *);
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void (*lav_mutex_spin_exit)(kmutex_t *);
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} mips_locore_atomicvec_t;
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void mips_set_wbflush(void (*)(void));
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void mips_wait_idle(void);
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void stacktrace(void);
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void logstacktrace(void);
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struct cpu_info;
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struct splsw;
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struct locoresw {
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void (*lsw_wbflush)(void);
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void (*lsw_cpu_idle)(void);
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int (*lsw_send_ipi)(struct cpu_info *, int);
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void (*lsw_cpu_offline_md)(void);
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void (*lsw_cpu_init)(struct cpu_info *);
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void (*lsw_cpu_run)(struct cpu_info *);
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int (*lsw_bus_error)(unsigned int);
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};
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struct mips_vmfreelist {
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paddr_t fl_start;
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paddr_t fl_end;
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int fl_freelist;
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};
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/*
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* The "active" locore-function vector, and
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*/
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extern const mips_locore_atomicvec_t mips_llsc_locore_atomicvec;
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extern mips_locore_atomicvec_t mips_locore_atomicvec;
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extern mips_locore_jumpvec_t mips_locore_jumpvec;
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extern struct locoresw mips_locoresw;
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struct splsw;
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struct mips_vmfreelist;
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struct phys_ram_seg;
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void mips64r2_vector_init(const struct splsw *);
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void mips_vector_init(const struct splsw *, bool);
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void mips_init_msgbuf(void);
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void mips_init_lwp0_uarea(void);
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void mips_page_physload(vaddr_t, vaddr_t,
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const struct phys_ram_seg *, size_t,
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const struct mips_vmfreelist *, size_t);
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/*
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* CPU identification, from PRID register.
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*/
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#define MIPS_PRID_REV(x) (((x) >> 0) & 0x00ff)
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#define MIPS_PRID_IMPL(x) (((x) >> 8) & 0x00ff)
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/* pre-MIPS32/64 */
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#define MIPS_PRID_RSVD(x) (((x) >> 16) & 0xffff)
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#define MIPS_PRID_REV_MIN(x) ((MIPS_PRID_REV(x) >> 0) & 0x0f)
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#define MIPS_PRID_REV_MAJ(x) ((MIPS_PRID_REV(x) >> 4) & 0x0f)
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/* MIPS32/64 */
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#define MIPS_PRID_CID(x) (((x) >> 16) & 0x00ff) /* Company ID */
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#define MIPS_PRID_CID_PREHISTORIC 0x00 /* Not MIPS32/64 */
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#define MIPS_PRID_CID_MTI 0x01 /* MIPS Technologies, Inc. */
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#define MIPS_PRID_CID_BROADCOM 0x02 /* Broadcom */
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#define MIPS_PRID_CID_ALCHEMY 0x03 /* Alchemy Semiconductor */
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#define MIPS_PRID_CID_SIBYTE 0x04 /* SiByte */
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#define MIPS_PRID_CID_SANDCRAFT 0x05 /* SandCraft */
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#define MIPS_PRID_CID_PHILIPS 0x06 /* Philips */
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#define MIPS_PRID_CID_TOSHIBA 0x07 /* Toshiba */
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#define MIPS_PRID_CID_MICROSOFT 0x07 /* Microsoft also, sigh */
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#define MIPS_PRID_CID_LSI 0x08 /* LSI */
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/* 0x09 unannounced */
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/* 0x0a unannounced */
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#define MIPS_PRID_CID_LEXRA 0x0b /* Lexra */
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#define MIPS_PRID_CID_RMI 0x0c /* RMI / NetLogic */
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#define MIPS_PRID_CID_CAVIUM 0x0d /* Cavium */
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#define MIPS_PRID_CID_INGENIC 0xe1
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#define MIPS_PRID_COPTS(x) (((x) >> 24) & 0x00ff) /* Company Options */
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#ifdef _KERNEL
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/*
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* Global variables used to communicate CPU type, and parameters
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* such as cache size, from locore to higher-level code (e.g., pmap).
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*/
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void mips_pagecopy(void *dst, void *src);
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void mips_pagezero(void *dst);
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#ifdef __HAVE_MIPS_MACHDEP_CACHE_CONFIG
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void mips_machdep_cache_config(void);
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#endif
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/*
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* trapframe argument passed to trap()
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*/
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#if 0
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#define TF_AST 0 /* really zero */
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#define TF_V0 _R_V0
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#define TF_V1 _R_V1
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#define TF_A0 _R_A0
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#define TF_A1 _R_A1
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#define TF_A2 _R_A2
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#define TF_A3 _R_A3
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#define TF_T0 _R_T0
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#define TF_T1 _R_T1
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#define TF_T2 _R_T2
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#define TF_T3 _R_T3
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#if defined(__mips_n32) || defined(__mips_n64)
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#define TF_A4 _R_A4
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#define TF_A5 _R_A5
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#define TF_A6 _R_A6
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#define TF_A7 _R_A7
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#else
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#define TF_T4 _R_T4
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#define TF_T5 _R_T5
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#define TF_T6 _R_T6
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#define TF_T7 _R_T7
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#endif /* __mips_n32 || __mips_n64 */
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#define TF_TA0 _R_TA0
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#define TF_TA1 _R_TA1
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#define TF_TA2 _R_TA2
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#define TF_TA3 _R_TA3
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#define TF_T8 _R_T8
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#define TF_T9 _R_T9
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#define TF_RA _R_RA
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#define TF_SR _R_SR
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#define TF_MULLO _R_MULLO
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#define TF_MULHI _R_MULLO
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#define TF_EPC _R_PC /* may be changed by trap() call */
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#define TF_NREGS (sizeof(struct reg) / sizeof(mips_reg_t))
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#endif
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struct trapframe {
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struct reg tf_registers;
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#define tf_regs tf_registers.r_regs
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uint32_t tf_ppl; /* previous priority level */
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mips_reg_t tf_pad; /* for 8 byte aligned */
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};
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CTASSERT(sizeof(struct trapframe) % (4*sizeof(mips_reg_t)) == 0);
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/*
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* Stack frame for kernel traps. four args passed in registers.
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* A trapframe is pointed to by the 5th arg, and a dummy sixth argument
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* is used to avoid alignment problems
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|
*/
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struct kernframe {
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#if defined(__mips_o32) || defined(__mips_o64)
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register_t cf_args[4 + 1];
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|
#if defined(__mips_o32)
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register_t cf_pad; /* (for 8 byte alignment) */
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#endif
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|
#endif
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|
#if defined(__mips_n32) || defined(__mips_n64)
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register_t cf_pad[2]; /* for 16 byte alignment */
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|
#endif
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|
register_t cf_sp;
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|
register_t cf_ra;
|
|
struct trapframe cf_frame;
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|
};
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|
|
|
CTASSERT(sizeof(struct kernframe) % (2*sizeof(mips_reg_t)) == 0);
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|
|
|
/*
|
|
* PRocessor IDentity TABle
|
|
*/
|
|
|
|
struct pridtab {
|
|
int cpu_cid;
|
|
int cpu_pid;
|
|
int cpu_rev; /* -1 == wildcard */
|
|
int cpu_copts; /* -1 == wildcard */
|
|
int cpu_isa; /* -1 == probed (mips32/mips64) */
|
|
int cpu_ntlb; /* -1 == unknown, 0 == probed */
|
|
int cpu_flags;
|
|
u_int cpu_cp0flags; /* presence of some cp0 regs */
|
|
u_int cpu_cidflags; /* company-specific flags */
|
|
const char *cpu_name;
|
|
};
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|
|
|
/*
|
|
* bitfield defines for cpu_cp0flags
|
|
*/
|
|
#define MIPS_CP0FL_USE __BIT(0) /* use these flags */
|
|
#define MIPS_CP0FL_ECC __BIT(1)
|
|
#define MIPS_CP0FL_CACHE_ERR __BIT(2)
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|
#define MIPS_CP0FL_EIRR __BIT(3)
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|
#define MIPS_CP0FL_EIMR __BIT(4)
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|
#define MIPS_CP0FL_EBASE __BIT(5)
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|
#define MIPS_CP0FL_CONFIG __BIT(6)
|
|
#define MIPS_CP0FL_CONFIG1 __BIT(7)
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|
#define MIPS_CP0FL_CONFIG2 __BIT(8)
|
|
#define MIPS_CP0FL_CONFIG3 __BIT(9)
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|
#define MIPS_CP0FL_CONFIG4 __BIT(10)
|
|
#define MIPS_CP0FL_CONFIG5 __BIT(11)
|
|
#define MIPS_CP0FL_CONFIG6 __BIT(12)
|
|
#define MIPS_CP0FL_CONFIG7 __BIT(13)
|
|
#define MIPS_CP0FL_USERLOCAL __BIT(14)
|
|
#define MIPS_CP0FL_HWRENA __BIT(15)
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|
|
|
/*
|
|
* cpu_cidflags defines, by company
|
|
*/
|
|
/*
|
|
* RMI company-specific cpu_cidflags
|
|
*/
|
|
#define MIPS_CIDFL_RMI_TYPE __BITS(2,0)
|
|
# define CIDFL_RMI_TYPE_XLR 0
|
|
# define CIDFL_RMI_TYPE_XLS 1
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|
# define CIDFL_RMI_TYPE_XLP 2
|
|
#define MIPS_CIDFL_RMI_THREADS_MASK __BITS(6,3)
|
|
# define MIPS_CIDFL_RMI_THREADS_SHIFT 3
|
|
#define MIPS_CIDFL_RMI_CORES_MASK __BITS(10,7)
|
|
# define MIPS_CIDFL_RMI_CORES_SHIFT 7
|
|
# define LOG2_1 0
|
|
# define LOG2_2 1
|
|
# define LOG2_4 2
|
|
# define LOG2_8 3
|
|
# define MIPS_CIDFL_RMI_CPUS(ncores, nthreads) \
|
|
((LOG2_ ## ncores << MIPS_CIDFL_RMI_CORES_SHIFT) \
|
|
|(LOG2_ ## nthreads << MIPS_CIDFL_RMI_THREADS_SHIFT))
|
|
# define MIPS_CIDFL_RMI_NTHREADS(cidfl) \
|
|
(1 << (((cidfl) & MIPS_CIDFL_RMI_THREADS_MASK) \
|
|
>> MIPS_CIDFL_RMI_THREADS_SHIFT))
|
|
# define MIPS_CIDFL_RMI_NCORES(cidfl) \
|
|
(1 << (((cidfl) & MIPS_CIDFL_RMI_CORES_MASK) \
|
|
>> MIPS_CIDFL_RMI_CORES_SHIFT))
|
|
#define MIPS_CIDFL_RMI_L2SZ_MASK __BITS(14,11)
|
|
# define MIPS_CIDFL_RMI_L2SZ_SHIFT 11
|
|
# define RMI_L2SZ_256KB 0
|
|
# define RMI_L2SZ_512KB 1
|
|
# define RMI_L2SZ_1MB 2
|
|
# define RMI_L2SZ_2MB 3
|
|
# define RMI_L2SZ_4MB 4
|
|
# define MIPS_CIDFL_RMI_L2(l2sz) \
|
|
(RMI_L2SZ_ ## l2sz << MIPS_CIDFL_RMI_L2SZ_SHIFT)
|
|
# define MIPS_CIDFL_RMI_L2SZ(cidfl) \
|
|
((256*1024) << (((cidfl) & MIPS_CIDFL_RMI_L2SZ_MASK) \
|
|
>> MIPS_CIDFL_RMI_L2SZ_SHIFT))
|
|
|
|
#endif /* _KERNEL */
|
|
#endif /* _MIPS_LOCORE_H */
|