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595 lines
13 KiB
C
595 lines
13 KiB
C
/* $NetBSD: cache_mipsNN.c,v 1.15 2015/05/20 07:04:49 matt Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache_mipsNN.c,v 1.15 2015/05/20 07:04:49 matt Exp $");
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#include <sys/param.h>
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#include <mips/cache.h>
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#include <mips/cache_r4k.h>
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#include <mips/cache_mipsNN.h>
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#include <mips/mipsNN.h>
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#include <uvm/uvm_extern.h>
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#define round_line16(x) (((x) + 15L) & -16L)
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#define trunc_line16(x) ((x) & -16L)
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#define round_line32(x) (((x) + 31L) & -32L)
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#define trunc_line32(x) ((x) & -32L)
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#ifdef SB1250_PASS1
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#define SYNC __asm volatile("sync; sync")
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#else
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#define SYNC __asm volatile("sync")
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#endif
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#ifdef __mips_o32
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__asm(".set mips32");
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#elif !defined(__mips64)
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__asm(".set mips64");
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#endif
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static int picache_stride;
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static int picache_loopcount;
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void
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mipsNN_cache_init(uint32_t config, uint32_t config1)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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bool flush_multiple_lines_per_way;
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flush_multiple_lines_per_way = mci->mci_picache_way_size > PAGE_SIZE;
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if (config & MIPSNN_CFG_VI) {
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/*
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* With a virtual Icache we don't need to flush
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* multiples of the page size with index ops; we just
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* need to flush one pages' worth.
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*/
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flush_multiple_lines_per_way = false;
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}
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if (flush_multiple_lines_per_way) {
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picache_stride = PAGE_SIZE;
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picache_loopcount = (mci->mci_picache_way_size / PAGE_SIZE) *
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mci->mci_picache_ways;
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} else {
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picache_stride = mci->mci_picache_way_size;
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picache_loopcount = mci->mci_picache_ways;
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}
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#define CACHE_DEBUG
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#ifdef CACHE_DEBUG
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if (config & MIPSNN_CFG_VI)
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printf(" icache is virtual\n");
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printf(" picache_stride = %d\n", picache_stride);
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printf(" picache_loopcount = %d\n", picache_loopcount);
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#endif
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}
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void
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mipsNN_icache_sync_all_16(void)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + mci->mci_picache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += (32 * 16);
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_all_32(void)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + mci->mci_picache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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mips_intern_dcache_wbinv_all();
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while (va < eva) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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va += (32 * 32);
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_16(vaddr_t va, vsize_t size)
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{
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vaddr_t eva;
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eva = round_line16(va + size);
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va = trunc_line16(va);
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 16)) {
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cache_r4k_op_32lines_16(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += 16;
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_32(vaddr_t va, vsize_t size)
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{
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vaddr_t eva;
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eva = round_line32(va + size);
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va = trunc_line32(va);
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mips_intern_dcache_wb_range(va, (eva - va));
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while ((eva - va) >= (32 * 32)) {
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cache_r4k_op_32lines_32(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += (32 * 32);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_I|CACHEOP_R4K_HIT_INV);
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va += 32;
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}
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SYNC;
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}
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void
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mipsNN_icache_sync_range_index_16(vaddr_t va, vsize_t size)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t eva, tmpva;
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int i, stride, loopcount;
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
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eva = round_line16(va + size);
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va = trunc_line16(va);
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/*
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* If we are going to flush more than is in a way, we are flushing
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* everything.
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*/
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if (eva - va >= mci->mci_picache_way_size) {
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mipsNN_icache_sync_all_16();
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return;
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}
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/*
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* GCC generates better code in the loops if we reference local
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* copies of these global variables.
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*/
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 16)) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride) {
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cache_r4k_op_8lines_16(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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}
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va += 8 * 16;
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}
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while (va < eva) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride) {
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cache_op_r4k_line(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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}
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va += 16;
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}
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}
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void
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mipsNN_icache_sync_range_index_32(vaddr_t va, vsize_t size)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t eva, tmpva;
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int i, stride, loopcount;
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va & mci->mci_picache_way_mask);
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eva = round_line32(va + size);
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va = trunc_line32(va);
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/*
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* If we are going to flush more than is in a way, we are flushing
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* everything.
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*/
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if (eva - va >= mci->mci_picache_way_size) {
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mipsNN_icache_sync_all_32();
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return;
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}
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/*
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* GCC generates better code in the loops if we reference local
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* copies of these global variables.
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*/
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stride = picache_stride;
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loopcount = picache_loopcount;
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mips_intern_dcache_wbinv_range_index(va, (eva - va));
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while ((eva - va) >= (8 * 32)) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride) {
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cache_r4k_op_8lines_32(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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}
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va += 8 * 32;
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}
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while (va < eva) {
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tmpva = va;
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for (i = 0; i < loopcount; i++, tmpva += stride) {
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cache_op_r4k_line(tmpva,
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CACHE_R4K_I|CACHEOP_R4K_INDEX_INV);
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}
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va += 32;
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}
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}
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void
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mipsNN_pdcache_wbinv_all_16(void)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + mci->mci_pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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while (va < eva) {
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cache_r4k_op_32lines_16(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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va += (32 * 16);
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}
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SYNC;
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}
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void
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mipsNN_pdcache_wbinv_all_32(void)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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vaddr_t va, eva;
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = va + mci->mci_pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the N different "ways".
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*/
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while (va < eva) {
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cache_r4k_op_32lines_32(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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va += (32 * 32);
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}
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SYNC;
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}
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void
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mipsNN_pdcache_wbinv_range_16(vaddr_t va, vsize_t size)
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{
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vaddr_t eva;
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eva = round_line16(va + size);
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va = trunc_line16(va);
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while ((eva - va) >= (32 * 16)) {
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cache_r4k_op_32lines_16(va,
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CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
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va += 16;
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}
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SYNC;
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}
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void
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mipsNN_pdcache_wbinv_range_32(vaddr_t va, vsize_t size)
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{
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vaddr_t eva;
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eva = round_line32(va + size);
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va = trunc_line32(va);
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while ((eva - va) >= (32 * 32)) {
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cache_r4k_op_32lines_32(va,
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CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
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va += (32 * 32);
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}
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while (va < eva) {
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cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB_INV);
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va += 32;
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}
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SYNC;
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}
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static void
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mipsNN_pdcache_wbinv_range_index_16_intern(vaddr_t va, vaddr_t eva)
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{
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va);
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eva = MIPS_PHYS_TO_KSEG0(eva);
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for (; (eva - va) >= (8 * 16); va += 8 * 16) {
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cache_r4k_op_8lines_16(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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}
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for (; va < eva; va += 16) {
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cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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}
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}
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static void
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mipsNN_pdcache_wbinv_range_index_32_intern(vaddr_t va, vaddr_t eva)
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{
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/*
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* Since we're doing Index ops, we expect to not be able
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* to access the address we've been given. So, get the
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* bits that determine the cache index, and make a KSEG0
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* address out of them.
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*/
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va = MIPS_PHYS_TO_KSEG0(va);
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eva = MIPS_PHYS_TO_KSEG0(eva);
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for (; (eva - va) >= (8 * 32); va += 8 * 32) {
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cache_r4k_op_8lines_32(va,
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CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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}
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for (; va < eva; va += 32) {
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cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_INDEX_WB_INV);
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}
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}
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void
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mipsNN_pdcache_wbinv_range_index_16(vaddr_t va, vsize_t size)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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const vaddr_t way_size = mci->mci_pdcache_way_size;
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const vaddr_t way_mask = way_size - 1;
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const u_int ways = mci->mci_pdcache_ways;
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vaddr_t eva;
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va &= way_mask;
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eva = round_line16(va + size);
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va = trunc_line16(va);
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/*
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* If we are going to flush more than is in a way, we are flushing
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* everything.
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*/
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if (eva - va >= way_size) {
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mipsNN_pdcache_wbinv_all_16();
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return;
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}
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/*
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* Invalidate each way. If the address range wraps past the end of
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* the way, we will be invalidating in two ways but eventually things
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* work out since the last way will wrap into the first way.
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*/
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for (u_int way = 0; way < ways; way++) {
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mipsNN_pdcache_wbinv_range_index_16_intern(va, eva);
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va += way_size;
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eva += way_size;
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}
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}
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void
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mipsNN_pdcache_wbinv_range_index_32(vaddr_t va, vsize_t size)
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{
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struct mips_cache_info * const mci = &mips_cache_info;
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const vaddr_t way_size = mci->mci_pdcache_way_size;
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const vaddr_t way_mask = way_size - 1;
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const u_int ways = mci->mci_pdcache_ways;
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vaddr_t eva;
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va &= way_mask;
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eva = round_line32(va + size);
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va = trunc_line32(va);
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/*
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* If we are going to flush more than is in a way, we are flushing
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* everything.
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*/
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if (eva - va >= way_size) {
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mipsNN_pdcache_wbinv_all_32();
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return;
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}
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/*
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* Invalidate each way. If the address range wraps past the end of
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* the way, we will be invalidating in two ways but eventually things
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* work out since the last way will wrap into the first way.
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*/
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for (u_int way = 0; way < ways; way++) {
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|
mipsNN_pdcache_wbinv_range_index_32_intern(va, eva);
|
|
va += way_size;
|
|
eva += way_size;
|
|
}
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_16(vaddr_t va, vsize_t size)
|
|
{
|
|
vaddr_t eva;
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
while ((eva - va) >= (32 * 16)) {
|
|
cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 16);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 16;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_inv_range_32(vaddr_t va, vsize_t size)
|
|
{
|
|
vaddr_t eva;
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_INV);
|
|
va += 32;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_16(vaddr_t va, vsize_t size)
|
|
{
|
|
vaddr_t eva;
|
|
|
|
eva = round_line16(va + size);
|
|
va = trunc_line16(va);
|
|
|
|
while ((eva - va) >= (32 * 16)) {
|
|
cache_r4k_op_32lines_16(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 16);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 16;
|
|
}
|
|
|
|
SYNC;
|
|
}
|
|
|
|
void
|
|
mipsNN_pdcache_wb_range_32(vaddr_t va, vsize_t size)
|
|
{
|
|
vaddr_t eva;
|
|
|
|
eva = round_line32(va + size);
|
|
va = trunc_line32(va);
|
|
|
|
while ((eva - va) >= (32 * 32)) {
|
|
cache_r4k_op_32lines_32(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += (32 * 32);
|
|
}
|
|
|
|
while (va < eva) {
|
|
cache_op_r4k_line(va, CACHE_R4K_D|CACHEOP_R4K_HIT_WB);
|
|
va += 32;
|
|
}
|
|
|
|
SYNC;
|
|
}
|