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286 lines
6.9 KiB
C
286 lines
6.9 KiB
C
/* $NetBSD: cache_tx39.c,v 1.7 2011/02/20 07:45:47 matt Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cache_tx39.c,v 1.7 2011/02/20 07:45:47 matt Exp $");
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#include <sys/param.h>
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#include <mips/cache.h>
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#include <mips/cache_tx39.h>
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#include <mips/locore.h>
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/*
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* Cache operations for TX3900/TX3920-style caches:
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*
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* - I-cache direct-mapped (TX3900) or 2-way set-associative (TX3920)
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* - D-cache 2-way set-associative
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* - Write-through (TX3900, TX3920) or write-back (TX3920)
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* - Physically indexed, phyiscally tagged
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*
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* XXX THIS IS NOT YET COMPLETE.
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*/
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#define round_line(x) (((x) + 15) & ~15)
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#define trunc_line(x) ((x) & ~15)
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void
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tx3900_icache_sync_all_16(void)
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{
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tx3900_icache_do_inv_index_16(MIPS_PHYS_TO_KSEG0(0),
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MIPS_PHYS_TO_KSEG0(mips_cache_info.mci_picache_size));
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}
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void
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tx3900_icache_sync_range_16(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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if ((eva - va) >= mips_cache_info.mci_picache_size) {
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/* Just hit the whole thing. */
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va = MIPS_PHYS_TO_KSEG0(0);
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eva = MIPS_PHYS_TO_KSEG0(mips_cache_info.mci_picache_size);
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}
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tx3900_icache_do_inv_index_16(va, eva);
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}
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#undef round_line
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#undef trunc_line
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#define round_line(x) (((x) + 3) & ~3)
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#define trunc_line(x) ((x) & ~3)
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static int tx3900_dummy_buffer[R3900_C_SIZE_MAX / sizeof(int)];
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void
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tx3900_pdcache_wbinv_all_4(void)
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{
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vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
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vaddr_t eva = va + mips_cache_info.mci_pdcache_size;
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volatile int *p;
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/*
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* No Index Invalidate for the TX3900 -- have to execute a
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* series of load instructions from the dummy buffer, instead.
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*/
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p = tx3900_dummy_buffer;
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while (va < eva) {
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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(void) *p++; (void) *p++; (void) *p++; (void) *p++;
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va += (32 * 4);
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}
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}
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void
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tx3900_pdcache_inv_range_4(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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while ((eva - va) >= (32 * 4)) {
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cache_tx39_op_32lines_4(va,
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CACHE_TX39_D|CACHEOP_TX3900_HIT_INV);
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va += (32 * 4);
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};
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while (va < eva) {
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cache_op_tx39_line(va, CACHE_TX39_D|CACHEOP_TX3900_HIT_INV);
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va += 4;
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}
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}
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void
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tx3900_pdcache_wb_range_4(vaddr_t va, vsize_t size)
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{
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/* Cache is write-through. */
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}
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#undef round_line
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#undef trunc_line
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#define round_line(x) (((x) + 15) & ~15)
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#define trunc_line(x) ((x) & ~15)
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void
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tx3920_icache_sync_all_16wb(void)
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{
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mips_dcache_wbinv_all();
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__asm volatile(".set push; .set mips2; sync; .set pop");
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tx3920_icache_do_inv_16(MIPS_PHYS_TO_KSEG0(0),
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MIPS_PHYS_TO_KSEG0(mips_cache_info.mci_picache_size));
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}
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void
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tx3920_icache_sync_range_16wt(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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tx3920_icache_do_inv_16(va, eva);
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}
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void
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tx3920_icache_sync_range_16wb(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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mips_dcache_wb_range(va, (eva - va));
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__asm volatile(".set push; .set mips2; sync; .set pop");
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tx3920_icache_do_inv_16(va, eva);
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}
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void
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tx3920_pdcache_wbinv_all_16wt(void)
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{
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vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
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vaddr_t eva = va + mips_cache_info.mci_pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the 2 different "ways".
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*/
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while (va < eva) {
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cache_tx39_op_32lines_16(va,
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CACHE_TX39_D|CACHEOP_TX3920_INDEX_INV);
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va += (32 * 16);
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}
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}
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void
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tx3920_pdcache_wbinv_all_16wb(void)
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{
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vaddr_t va = MIPS_PHYS_TO_KSEG0(0);
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vaddr_t eva = va + mips_cache_info.mci_pdcache_size;
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/*
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* Since we're hitting the whole thing, we don't have to
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* worry about the 2 different "ways".
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*/
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while (va < eva) {
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cache_tx39_op_32lines_16(va,
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CACHE_TX39_D|CACHEOP_TX3920_INDEX_WB_INV);
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va += (32 * 16);
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}
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}
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void
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tx3920_pdcache_wbinv_range_16wb(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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while ((eva - va) >= (32 * 16)) {
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cache_tx39_op_32lines_16(va,
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CACHE_TX39_D|CACHEOP_TX3920_HIT_WB_INV);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_tx39_line(va, CACHE_TX39_D|CACHEOP_TX3920_HIT_WB_INV);
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va += 16;
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}
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}
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void
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tx3920_pdcache_inv_range_16(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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while ((eva - va) >= (32 * 16)) {
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cache_tx39_op_32lines_16(va,
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CACHE_TX39_D|CACHEOP_TX3920_HIT_INV);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_tx39_line(va, CACHE_TX39_D|CACHEOP_TX3920_HIT_INV);
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va += 16;
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}
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}
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void
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tx3920_pdcache_wb_range_16wt(vaddr_t va, vsize_t size)
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{
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/* Cache is write-through. */
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}
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void
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tx3920_pdcache_wb_range_16wb(vaddr_t va, vsize_t size)
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{
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vaddr_t eva = round_line(va + size);
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va = trunc_line(va);
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while ((eva - va) >= (32 * 16)) {
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cache_tx39_op_32lines_16(va,
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CACHE_TX39_D|CACHEOP_TX3920_HIT_WB);
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va += (32 * 16);
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}
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while (va < eva) {
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cache_op_tx39_line(va, CACHE_TX39_D|CACHEOP_TX3920_HIT_WB);
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va += 16;
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}
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}
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