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103 lines
3.3 KiB
C
103 lines
3.3 KiB
C
/* $NetBSD: rmixl_pcievar.h,v 1.3 2011/02/20 07:48:37 matt Exp $ */
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/*-
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* Copyright (c) 2010 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Cliff Neighbors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_RMI_PCIE_VAR_H_
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#define _MIPS_RMI_PCIE_VAR_H_
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#include <dev/pci/pcivar.h>
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typedef enum rmixl_pcie_lnkcfg_mode {
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LCFG_NO=0, /* placeholder */
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LCFG_EP, /* end point */
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LCFG_RC, /* root complex */
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} rmixl_pcie_lnkcfg_mode_t;
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typedef struct rmixl_pcie_lnkcfg {
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rmixl_pcie_lnkcfg_mode_t mode;
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u_int lanes;
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} rmixl_pcie_lnkcfg_t;
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typedef struct rmixl_pcie_lnktab {
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u_int ncfgs;
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const char *str;
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const rmixl_pcie_lnkcfg_t *cfg;
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} rmixl_pcie_lnktab_t;
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typedef struct rmixl_pcie_evcnt {
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struct evcnt evcnt;
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char name[32];
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} rmixl_pcie_evcnt_t;
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typedef struct rmixl_pcie_link_dispatch {
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int (*func)(void *);
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void *arg;
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u_int link;
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u_int bitno;
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u_int irq;
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rmixl_pcie_evcnt_t *counts; /* index by cpu */
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} rmixl_pcie_link_dispatch_t;
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struct rmixl_pcie_softc;
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typedef struct rmixl_pcie_link_intr {
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struct rmixl_pcie_softc *sc;
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u_int link;
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u_int ipl;
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void *ih; /* mips interrupt handle */
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callout_t callout; /* for delayed free of this struct */
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u_int dispatch_count;
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rmixl_pcie_link_dispatch_t dispatch_data[1];
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/* variable length */
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} rmixl_pcie_link_intr_t;
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#define RMIXL_PCIE_NLINKS_MAX 4
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typedef struct rmixl_pcie_softc {
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device_t sc_dev;
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struct mips_pci_chipset sc_pci_chipset;
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bus_space_tag_t sc_pci_cfg_memt;
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bus_space_tag_t sc_pci_ecfg_memt;
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bus_dma_tag_t sc_29bit_dmat;
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bus_dma_tag_t sc_32bit_dmat;
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bus_dma_tag_t sc_64bit_dmat;
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rmixl_pcie_lnktab_t sc_pcie_lnktab;
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kmutex_t sc_mutex;
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int sc_tmsk;
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void *sc_fatal_ih;
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rmixl_pcie_evcnt_t *sc_evcnts[RMIXL_PCIE_NLINKS_MAX];
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rmixl_pcie_link_intr_t *sc_link_intr[RMIXL_PCIE_NLINKS_MAX];
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} rmixl_pcie_softc_t;
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extern void rmixl_physaddr_init_pcie(struct extent *);
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#endif /* _MIPS_RMI_PCIE_VAR_H_ */
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