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113 lines
3.9 KiB
C
113 lines
3.9 KiB
C
/* $NetBSD: sbbuswatch.c,v 1.2 2011/02/20 07:47:39 matt Exp $ */
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/*
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* Copyright (c) 2010, The NetBSD Foundation, Inc. All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Cliff Neighbors.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/cpu.h>
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#include <mips/cpu.h>
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#include <mips/locore.h>
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#include <mips/sibyte/include/sb1250_int.h>
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#include <mips/sibyte/include/sb1250_regs.h>
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#include <mips/sibyte/dev/sbbuswatchvar.h>
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#define READ_REG(rp) (mips3_ld((volatile uint64_t *)(rp)))
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#define WRITE_REG(rp, val) (mips3_sd((volatile uint64_t *)(rp), (val)))
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static void sibyte_bus_watch_intr(void *, uint32_t, vaddr_t);
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void
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sibyte_bus_watch_init(void)
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{
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(void)READ_REG(MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
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WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
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WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
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(void)cpu_intr_establish(K_INT_BAD_ECC, IPL_DDB,
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sibyte_bus_watch_intr, (void *)K_INT_BAD_ECC);
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(void)cpu_intr_establish(K_INT_COR_ECC, IPL_DDB,
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sibyte_bus_watch_intr, (void *)K_INT_COR_ECC);
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(void)cpu_intr_establish(K_INT_IO_BUS, IPL_DDB,
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sibyte_bus_watch_intr, (void *)K_INT_IO_BUS);
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}
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int
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sibyte_bus_watch_check(unsigned int cause)
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{
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uint64_t err_ctl;
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uint64_t cache_err_i;
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uint64_t cache_err_d;
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uint64_t cache_err_dpa;
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uint64_t bus_err_dpa;
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uint32_t bus_err_status;
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uint32_t l2_errors;
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uint32_t mem_io_errors;
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bus_err_status = READ_REG(
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MIPS_PHYS_TO_KSEG1(A_SCD_BUS_ERR_STATUS));
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if (bus_err_status == 0)
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return 0;
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l2_errors = READ_REG(
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MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS));
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if (l2_errors != 0)
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WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_L2_ERRORS), 0);
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mem_io_errors = READ_REG(
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MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS));
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if (mem_io_errors != 0)
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WRITE_REG(MIPS_PHYS_TO_KSEG1(A_BUS_MEM_IO_ERRORS), 0);
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asm volatile("dmfc0 %0, $26, 0;" : "=r"(err_ctl));
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asm volatile("dmfc0 %0, $26, 1;" : "=r"(bus_err_dpa));
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asm volatile("dmfc0 %0, $27, 0;" : "=r"(cache_err_i));
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asm volatile("dmfc0 %0, $27, 1;" : "=r"(cache_err_d));
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asm volatile("dmfc0 %0, $27, 3;" : "=r"(cache_err_dpa));
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printf("bus_err_status=%#x\n", bus_err_status);
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printf("l2_errors=%#x\n", l2_errors);
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printf("mem_io_errors=%#x\n", mem_io_errors);
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printf("err_ctl=%#"PRIx64"\n", err_ctl);
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printf("bus_err_dpa=%#"PRIx64"\n", bus_err_dpa);
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printf("cache_err_i=%#"PRIx64"\n", cache_err_i);
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printf("cache_err_d=%#"PRIx64"\n", cache_err_d);
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printf("cache_err_dpa=%#"PRIx64"\n", cache_err_dpa);
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return -1;
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}
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static void
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sibyte_bus_watch_intr(void *arg, uint32_t status, vaddr_t pc)
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{
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printf("%s: %p\n", __func__, arg);
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(void)sibyte_bus_watch_check(0);
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}
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