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54 lines
2.5 KiB
C
54 lines
2.5 KiB
C
/* $NetBSD: ctlreg.h,v 1.1 2009/02/10 06:04:56 rumble Exp $ */
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/*
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* Copyright (c) 2009 Stephen M. Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_DEV_CTLREG_H_
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#define _ARCH_SGIMIPS_DEV_CTLREG_H_
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#define CTL_MEMCFG 0x00000000 /* Memory configuration (8) */
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#define CTL_SYSID 0x00000001 /* System ID (8) */
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#define CTL_SYSID_FPU 0x02 /* FPU present */
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#define CTL_CPUCTRL 0x00080002 /* Misc. config bits (16) */
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#define CTL_CPUCTRL_SYSRESET 0x0200 /* VME SYSRESET: reset system */
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#define CTL_CPUCTRL_PARITY 0x0400 /* Enable parity checking */
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#define CTL_CPUCTRL_SLAVE 0x0800 /* Enable slave accesses */
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#define CTL_CPUCTRL_WDOG 0x4000 /* Watchdog enable */
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#define CTL_LAN_PAR_CLR 0x002a0000 /* Clear LAN parity error (8) */
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#define CTL_DMA_PAR_CLR 0x002a0001 /* Clear DMA parity error (8) */
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#define CTL_CPU_PAR_CLR 0x002a0002 /* Clear CPU parity error (8) */
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#define CTL_VME_PAR_CLR 0x002a0003 /* Clear VME parity error (8) */
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#define CTL_AUX_CPUCTRL 0x000e0000 /* Aux. cpu control reg (8) */
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#define CTL_AUX_CPUCTRL_CONSLED 0x10 /* Enable console led */
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#define CTL_AUX_CPUCTRL_HRTBEAT 0x01 /* Heartbeat */
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#endif /* _ARCH_SGIMIPS_DEV_CTLREG_H_ */
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