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50 lines
2.1 KiB
C
50 lines
2.1 KiB
C
/* $NetBSD: int1reg.h,v 1.2 2009/02/12 06:33:57 rumble Exp $ */
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/*
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* Copyright (c) 2009 Stephen M. Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#if !defined(_ARCH_SGIMIPS_DEV_INT1REG_H_)
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#define _ARCH_SGIMIPS_DEV_INT1REG_H_
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/* The INT has known locations on all SGI machines */
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#define INT1_IP6_IP10 0x1f980000
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/*
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* NB: The STATUS register is backwards w.r.t. INT2: a bit set implies
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* no pending interrupt. The MASK register is like INT2: a bit
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* set implies that the interrupt is enabled.
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*/
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#define INT1_LOCAL_STATUS 0x000002 /* 16-bit */
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#define INT1_LOCAL_MASK 0x00000b /* 8-bit */
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/* i8254 is actually its own chip, but we can pretend to be like INT2... */
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#define INT1_TIMER_0_ACK 0x0a0000 /* 8-bit */
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#define INT1_TIMER_1_ACK 0x080000 /* 8-bit */
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#define INT1_TIMER_0 0x1c0000 /* 8-bit */
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#define INT1_TIMER_1 0x1c0004 /* 8-bit */
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#define INT1_TIMER_2 0x1c0008 /* 8-bit */
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#define INT1_TIMER_CONTROL 0x1c000c /* 8-bit */
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#endif /* _ARCH_SGIMIPS_DEV_INT1REG_H_ */
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