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107 lines
4.5 KiB
C
107 lines
4.5 KiB
C
/* $NetBSD: oiocreg.h,v 1.1 2009/02/10 06:04:56 rumble Exp $ */
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/*
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* Copyright (c) 2009 Stephen M. Rumble
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_DEV_OIOCREG_H_
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#define _ARCH_SGIMIPS_DEV_OIOCREG_H_
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/* Registers below are relative to: */
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#define OIOC_BASE_ADDRESS 0x1f900000
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/*
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* The IOC SCSI DMA engine consists of 257 16-bit address registers, which can
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* point to 256 4096-byte buffers.
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*
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* IOC_SCSI_DMA_LOW contains the first 12 bits of a starting offset within
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* the first page of a virtually contiguous buffer. The MSB indicates DMA
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* transfer direction.
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*
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* There are 256 high address registers starting at IOC_SCSI_DMA_HIGH_BASE
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* and occurring every 4 bytes. This provides 28 address bits - more than
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* sufficient for these old machines.
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*/
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#define OIOC_SCSI_REGS 0x00000000 /* SCSI registers offset */
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#define OIOC_SCSI_REGS_SIZE 0x00200102 /* SCSI length */
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#define OIOC_SCSI_DMA_LOW 0x00000002 /* 16-bit */
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#define OIOC_SCSI_DMA_HIGH_BASE 0x00020002 /* 16-bit */
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#define OIOC_SCSI_DMA_FLUSH 0x00040000 /* 32-bit; write 0 to flush */
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#define OIOC_SCSI_DMA_NSEGS 256
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#define OIOC_SCSI_DMA_HIGH(_x) (OIOC_SCSI_DMA_HIGH_BASE + ((_x) << 2))
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#define OIOC_SCSI_DMA_HIGH_SHFT 12
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#define OIOC_SCSI_DMA_LOW_ADDR_MASK 0x0fff
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#define OIOC_SCSI_DMA_LOW_ADDR_DMADIR 0x8000 /* if set: SCSI->MEM */
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#define OIOC_SCSI_RESET_OFF 0x00180000 /* 32-bit; read to set _RESET */
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#define OIOC_SCSI_RESET_ON 0x00180004 /* 32-bit; read to clr _RESET */
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#define OIOC_WD33C93_ASR 0x00200001 /* 8-bit; scsi asr register */
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#define OIOC_WD33C93_ASR_SIZE 1
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#define OIOC_WD33C93_DATA 0x00200101 /* 8-bit; scsi data register */
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#define OIOC_WD33C93_DATA_SIZE 1
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/*
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* IOC has 64 (I think) 16-bit page remap registers occurring every 4 bytes
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* starting at 0xbf920802. Each register takes a physical page number, N, which
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* maps physical memory page N into LANCE's 24-bit address space at offset
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* (N * 4096).
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*/
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#define OIOC_ENET_PGMAP_BASE 0x00020802 /* 16-bit */
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#define OIOC_ENET_NPGMAPS 64 /* 64 pages */
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#define OIOC_ENET_PGMAP_SIZE (OIOC_ENET_NPGMAPS * 4)
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#define OIOC_ENET_PGMAP_OFF(n) ((n) << 2) /* every 4 bytes */
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#define OIOC_ENET_RESET_OFF 0x00060000 /* 8-bit; read to set _RESET */
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#define OIOC_ENET_RESET_ON 0x00060004 /* 8-bit; read to clr _RESET */
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#define OIOC_LANCE_RDP 0x00050000 /* 16-bit; le reg. data port */
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#define OIOC_LANCE_RDP_SIZE 2
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#define OIOC_LANCE_RAP 0x00050100 /* 16-bit; le reg. access port*/
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#define OIOC_LANCE_RAP_SIZE 2
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#define OIOC2_CONFIG 0x00180008 /* 32-bit; IOC2 (IP6/10) only */
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/* OIOC2_CONFIG bits; only BURST, NOSYNC and HIWAT are writable. */
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#define OIOC2_CONFIG_HIWAT_MASK 0x0000000f
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#define OIOC2_CONFIG_HIWAT_SHFT 0x00000000
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#define OIOC2_CONFIG_ID_MASK 0x00000030
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#define OIOC2_CONFIG_ID_SHFT 0x00000004
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#define OIOC2_CONFIG_NOSYNC_MASK 0x00000040
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#define OIOC2_CONFIG_NOSYNC_SHFT 0x00000006
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#define OIOC2_CONFIG_BURST_MASK 0x00000080
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#define OIOC2_CONFIG_BURST_SHFT 0x00000007
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#define OIOC2_CONFIG_COUNT_MASK 0x00007f00
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#define OIOC2_CONFIG_COUNT_SHFT 0x00000008
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#define OIOC2_CONFIG_RSRVD_MASK 0x00008000
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#define OIOC2_CONFIG_RSRVD_SHFT 0x0000000f
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#define OIOC2_CONFIG_SCP_MASK 0x003f0000
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#define OIOC2_CONFIG_SCP_SHFT 0x00000010
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#define OIOC2_CONFIG_RSRVD2_MASK 0x0fc00000
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#define OIOC2_CONFIG_RSRVD2_SHFT 0x00000016
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#define OIOC2_CONFIG_IOP_MASK 0xf0000000
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#define OIOC2_CONFIG_IOP_SHFT 0x0000001c
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#endif /* _ARCH_SGIMIPS_DEV_OIOCREG_H_ */
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