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102 lines
3.5 KiB
C
102 lines
3.5 KiB
C
/* $NetBSD: intr.h,v 1.12 2012/07/27 05:36:11 matt Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Paul Kranenburg.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Device class interrupt levels
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* Note: sun4 and sun4c hardware only has software interrupt available
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* on level 1, 4 or 6. This limits the choice of the various
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* IPL_SOFT* symbols to one of those three values.
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*/
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#define IPL_NONE 0 /* nothing */
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#define IPL_SOFTCLOCK 1 /* timeouts */
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#define IPL_SOFTNET 1 /* protocol stack */
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#define IPL_SOFTBIO 1 /* block I/O */
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#define IPL_SOFTAUDIO 4 /* second-level audio */
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#define IPL_SOFTFDC 4 /* second-level floppy */
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#define IPL_SOFTSERIAL 6 /* serial */
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#define IPL_VM 7 /* memory allocation */
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#define IPL_SCHED 11 /* scheduler */
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#define IPL_HIGH 15 /* everything */
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/*
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* fd hardware, ts102, and tadpole microcontoller interrupts are at level 11
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*/
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#define IPL_FD IPL_SCHED
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#define IPL_TS102 IPL_SCHED
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/*
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* zs hardware interrupts are at level 12
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* su (com) hardware interrupts are at level 13
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* IPL_SERIAL must protect them all.
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*/
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#define IPL_ZS IPL_HIGH
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/*
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* IPL_SAFEPRI is a safe priority for sleep to set for a spin-wait
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* during autoconfiguration or after a panic.
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*/
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#define IPL_SAFEPRI 0
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#if defined(_KERNEL) && !defined(_LOCORE)
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void *
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sparc_softintr_establish(int level, void (*fun)(void *), void *arg);
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void
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sparc_softintr_disestablish(void *cookie);
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/*
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* NB that sparc_softintr_schedule() casts the cookie to an int *.
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* This is to get the sic_pilreq member of the softintr_cookie
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* structure, which is otherwise internal to intr.c.
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*/
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#if defined(SUN4M) || defined(SUN4D)
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extern void raise(int, int);
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#if !(defined(SUN4) || defined(SUN4C))
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#define sparc_softintr_schedule(cookie) raise(0, *((int *) (cookie)))
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#else /* both defined */
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#define sparc_softintr_schedule(cookie) do { \
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if (CPU_ISSUN4M || CPU_ISSUN4D) \
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raise(0, *((int *)(cookie))); \
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else \
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ienab_bis(*((int *)(cookie))); \
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} while (0)
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#endif /* SUN4 || SUN4C */
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#else /* SUN4M || SUN4D */
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#define sparc_softintr_schedule(cookie) ienab_bis(*((int *) (cookie)))
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#endif /* SUN4M || SUN4D */
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#if 0
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void sparc_softintr_schedule(void *cookie);
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#endif
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#endif /* KERNEL && !_LOCORE */
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