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259 lines
12 KiB
C
259 lines
12 KiB
C
/*-
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* Copyright (C) 2001-2003 by NBMK Encryption Technologies.
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* All rights reserved.
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*
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* NBMK Encryption Technologies provides no support of any kind for
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* this software. Questions or concerns about it may be addressed to
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* the members of the relevant open-source community at
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* <tech-crypto@netbsd.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*****************************************************************************
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* @(#) nsp2000_regs.h 1.9@(#)
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*****************************************************************************/
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/*****************************************************************************/
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/** @file nsp2000_regs.h
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* @brief NSP2000 Control Register Layout
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*
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* This header contains a structure that maps all NSP2000 control registers
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* for the 4 major subcomponents - the AMBA controller, the PKE/PKH,
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* the RNG/RNH, and the CCH/CC.
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*
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*****************************************************************************/
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/*****************************************************************************
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* Revision history:
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* 01/16/04 jpw Add N8_NO_64_BURST to prevent 64bit bursts to 32 bit regs
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* during sequential slave io accesses. Certain chipsets
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* need this for proper use with the PCI-X board.
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* 03/01/02 brr Added register definition previously in n8_enqueue_common.h
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* 01/15/02 dkm Added amba read pointer mirror register and fixed comment.
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* BUG 413
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* 11/12/01 msz Made uint32_t's vuint32_t's (volatile). Fix for BUG 281.
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* 09/07/01 mmd Further elimination of "simon" except for line 155, which
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* is there until the rest of the SDK has been updated to use
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* NSP2000REGS_t instead of SIMON.
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* 08/16/01 mmd Elimination of "simon" and relocation to driver/common.
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* 08/01/01 mmd Migration to new common driver framework.
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* 07/25/01 mmd Now including stdint.h for Linux, to get uint32_t types.
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* 07/19/01 mmd Cleaned up the #include's at top of file.
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* 06/27/01 jke changed #ifdef protections on #include bsdi_types.h so file
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* can be included in both BSDi kernel and user-apps
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* 06/21/01 jke added #include ../bsdi_types.h to ensure compile-ability in
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* BSD
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* 06/21/01 mmd Ensuring inttypes.h doesn't get included when building the
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* Linux or BSDi drivers. One should, in either of these cases,
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* define either the LINUXDRIVER or BSDIDRIVER symbol in the
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* driver's makefile.
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* 06/06/01 mmd Added missing amba_pci_timer_value register, and all CCH
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* registers. Also reformatted.
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* 01/03/01 jw Original version.
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****************************************************************************/
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/** @defgroup NSP2000Driver NSP2000 Control Register Layout.
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*/
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#ifndef NSP2000_REGS_H
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#define NSP2000_REGS_H
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#include "n8_pub_types.h"
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typedef volatile uint8_t vuint8_t;
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typedef volatile uint16_t vuint16_t;
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typedef volatile uint32_t vuint32_t;
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#define NSP_CORE_ENABLE 0x80000000
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#define NSP_CORE_BUSY 0x40000000
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/* This dummy write breaks up sequential register accesses */
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/* Sequential accesses may fail on the PCI-X board on some */
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/* chipsets if the system attempts to turn two 32 bit */
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/* register accesses into a single 64 byte burst. */
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#define N8_NO_64_BURST nsp->amba_pci_test=0xbadbeef;
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/****************************************************
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* 64K of total address space *
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* *
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* In PCI BAR0 - Offset from hw pointer: *
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* 0x0000 - 16K - AMBA-PCI Bridge *
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* 0x4000 - 16K - Public Key Module *
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* 0x8000 - 16K - Crypto Control Processor *
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* 0xC000 - 16K - Random Number Generator *
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****************************************************/
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#define PKE_REG_OFFSET 0x4000
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#define EA_REG_OFFSET 0x8000
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#define RNG_REG_OFFSET 0xC000
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typedef struct
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{
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/* AMBA CONTROLLER REGISTERS */
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vuint32_t amba_pci_endian_mode; /* 0000 */
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vuint32_t amba_pci_timer_preset; /* 0004 */
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vuint32_t amba_pci_status; /* 0008 */
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vuint32_t amba_pci_control; /* 000C */
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vuint32_t amba_pci_timer_value; /* 0010 */
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vuint32_t amba_pci_test; /* 0014 */
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vuint32_t amba_pci_read_ptr_mirror; /* 0018 */
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vuint32_t amba_pci_unused[4089]; /* 001C */
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/* PKH AND PKE REGISTERS */
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vuint32_t pkh_test0; /* 4000 */
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vuint32_t pkh_test1; /* 4004 */
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vuint32_t pkh_q_length; /* 4008 */
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vuint32_t pkh_q_ptr; /* 400C */
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vuint32_t pkh_q_bar1; /* 4010 */
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vuint32_t pkh_q_bar0; /* 4014 */
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vuint32_t pkh_intr_enable; /* 4018 */
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vuint32_t pkh_control_status; /* 401C */
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vuint32_t pkh_secure_key_storage_data; /* 4020 */
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vuint32_t pkh_secure_key_storage_control;/* 4024 */
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vuint32_t pkh_reserved[46]; /* 4028 */
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vuint32_t pke_command_block[8]; /* 40E0 */
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vuint32_t pkh_reserved1[960]; /* 4100 */
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vuint32_t pke_BN_cache[1024]; /* 5000 */ /* 256 "digits" */
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/* of 128 bits */
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vuint32_t pkh_reserved2[2048]; /* 6000 */
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/* CCH REGISTERS */
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vuint32_t cch_test0; /* 8000 */
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vuint32_t cch_test1; /* 8004 */
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vuint32_t cch_q_length; /* 8008 */
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vuint32_t cch_q_ptr; /* 800C */
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vuint32_t cch_q_bar1; /* 8010 */
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vuint32_t cch_q_bar0; /* 8014 */
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vuint32_t cch_intr_enable; /* 8018 */
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vuint32_t cch_control_status; /* 801C */
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vuint32_t cch_context_data1; /* 8020 */
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vuint32_t cch_context_data0; /* 8024 */
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vuint32_t cch_context_addr; /* 8028 */
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vuint32_t cch_reserved[4085]; /* 802C */
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/* RNG REGISTERS - RNG Buffer - RNH REGISTERS */
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/* 64-bit registers in the RNG must be read/written using the Most */
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/* Significant Word first, in order to access the full 64bit value. */
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vuint32_t rng_reserved0; /* C000 */
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vuint32_t rng_tod_seconds; /* C004 */
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vuint32_t rng_reserved1; /* C008 */
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vuint32_t rng_tod_prescale; /* C00C */
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vuint32_t rng_tod_msw; /* C010 */
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vuint32_t rng_tod_lsw; /* C014 */
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vuint32_t rng_key1_msw; /* C018 */
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vuint32_t rng_key1_lsw; /* C01C */
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vuint32_t rng_key2_msw; /* C020 */
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vuint32_t rng_key2_lsw; /* C024 */
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vuint32_t rng_hostseed_msw; /* C028 */
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vuint32_t rng_hostseed_lsw; /* C02C */
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vuint32_t rng_reserved2; /* C030 */
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vuint32_t rng_sample_interval; /* C034 */
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vuint32_t rng_reserved3; /* C038 */
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vuint32_t rng_external_clock_scalar; /* C03C */
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vuint32_t rng_reserved4; /* C040 */
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vuint32_t rng_buffer_write_ptr; /* C044 */
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vuint32_t rng_sample_seed_msw; /* C048 */
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vuint32_t rng_sample_seed_lsw; /* C04C */
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vuint32_t rng_reserved5; /* C050 */
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vuint32_t rng_lsfr_diag; /* C054 */
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vuint32_t rng_lsfr1_history_msw; /* C058 */
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vuint32_t rng_lsfr1_history_lsw; /* C05C */
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vuint32_t rng_lsfr2_history_msw; /* C060 */
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vuint32_t rng_lsfr2_history_lsw; /* C064 */
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vuint32_t rng_lsfr3_history_msw; /* C068 */
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vuint32_t rng_lsfr3_history_lsw; /* C06C */
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vuint32_t rng_lsfr4_history_msw; /* C070 */
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vuint32_t rng_lsfr4_history_lsw; /* C074 */
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vuint32_t rng_reserved6; /* C078 */
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vuint32_t rng_control_status; /* C07C */
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vuint32_t rng_reserved7[480]; /* C080 */
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vuint32_t rng_buffer[512]; /* This buffer is to be */
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/* interpreted as 256 64-bit */
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/* value. Software must */
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/* access MSB first - 0 then */
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/* 1. */
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vuint32_t rnh_test1; /* D000 */
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vuint32_t rnh_test0; /* D004 */
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vuint32_t rnh_q_length; /* D008 */
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vuint32_t rnh_q_ptr; /* D00C */
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vuint32_t rnh_q_bar1; /* D010 */
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vuint32_t rnh_q_bar0; /* D014 */
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vuint32_t rnh_control_status; /* D018 */
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vuint32_t rnh_reserved; /* D01C */
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vuint32_t rng_unused[3064]; /* D020 */
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} NSP2000REGS_t;
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typedef NSP2000REGS_t SIMON;
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typedef struct
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{
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/* Common Registers */
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volatile uint32_t test0; /* 0000 */
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volatile uint32_t test1; /* 0004 */
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volatile uint32_t q_length; /* 0008 */
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volatile uint32_t q_ptr; /* 000C */
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volatile uint32_t q_bar1; /* 0010 */
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volatile uint32_t q_bar0; /* 0014 */
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volatile uint32_t intr_enable; /* 0018 */
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volatile uint32_t control_status; /* 001C */
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} N8CommonRegs_t;
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typedef struct
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{
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N8CommonRegs_t commonRegs;
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volatile uint32_t pkh_secure_key_storage_data; /* 0020 */
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volatile uint32_t pkh_secure_key_storage_control;/* 0024 */
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volatile uint32_t pkh_reserved[46]; /* 0028 */
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volatile uint32_t pke_command_block[8]; /* 00E0 */
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volatile uint32_t pkh_reserved1[960]; /* 0100 */
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volatile uint32_t pke_BN_cache[1024]; /* 0000 */ /* 256 "digits" */
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/* of 128 bits */
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} N8PKERegs_t;
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/* CCH REGISTERS */
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typedef struct
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{
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N8CommonRegs_t commonRegs;
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volatile uint32_t cch_context_data1; /* 0020 */
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volatile uint32_t cch_context_data0; /* 0024 */
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volatile uint32_t cch_context_addr; /* 0028 */
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} N8EARegs_t;
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#define N8_SetDebugRegister(x, y) {x->amba_pci_unused[58] = y;}
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#endif /* NSP2000_REGS_H */
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