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175 lines
4.9 KiB
Groff
175 lines
4.9 KiB
Groff
.\" $NetBSD: apic.4,v 1.1 2011/06/06 16:52:15 jruoho Exp $
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.\"
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.\" Copyright (c) 2011 Jukka Ruohonen <jruohonen@iki.fi>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Neither the name of the author nor the names of any
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.\" contributors may be used to endorse or promote products derived
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.\" from this software without specific prior written permission.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS
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.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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.\" POSSIBILITY OF SUCH DAMAGE.
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.\"
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.Dd June 6, 2011
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.Dt APIC 4 x86
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.Os
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.Sh NAME
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.Nm apic ,
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.Nm ioapic ,
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.Nm lapic
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.Nd Intel APIC Architecture
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.Sh SYNOPSIS
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.Cd "ioapic* at mainbus*"
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.Sh DESCRIPTION
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The
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.Nm
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subsystem provides basis for a system of advanced programmable
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interrupt controllers
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.Pq Tn APICs
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originally designed by Intel but now widely used on all x86 systems.
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.Pp
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There are two elements in the architecture, the local
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.Tn APIC
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.Pq Tn LAPIC
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and the
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.Tn I/O APIC .
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Historically these were connected by a dedicated 3-wire
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.Dq APIC bus ,
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but the system bus is used for communication today.
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The configuration is increasingly dependent on
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.Tn ACPI .
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.Pp
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Typically each
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.Tn CPU
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in the system contains one
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.Tn LAPIC
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that performs two primary functions:
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.Bl -enum -offset indent
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.It
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It receives interrupts both from internal sources and from the external
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.Tn I/O APIC .
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The interrupt sources include
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.Tn I/O
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devices, the programmable
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.Tn APIC
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timer, performance monitoring counters,
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thermal sensor interrupts, and others.
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.It
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In multiprocessor
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.Pq Tn MP
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systems a
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.Tn LAPIC
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receives and sends interprocessor interrupts
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.Pq Tn IPIs
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from and to other processors in the system.
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.Tn IPIs
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are used to provide software interrupts,
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interrupt forwarding, or preemptive scheduling.
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Against this, the architecture can be generally seen as an attempt
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to solve the interrupt routing efficiency issues in
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.Tn MP
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systems.
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.El
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.Pp
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There is typically one
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.Tn I/O APIC
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for each peripheral bus in the system.
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Each
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.Tn I/O APIC
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has a series of interrupt inputs to external interrupt sources.
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The architecture usually contains a redirection table which can be used
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to route the interrupts that an
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.Tn I/O APIC
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receives to one or more local
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.Tn APICs .
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When a
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.Tn LAPIC
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is able to accept an interrupt, it will signal the
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.Tn CPU .
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Without an
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.Tn I/O APIC ,
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the local
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.Tn APICs
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are therefore mostly useless; one of the primary functions
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of the architecture is no longer achievable, interrupts can
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not be distributed to different
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.Tn CPUs .
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.Pp
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The 8259
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.Tn PIC
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has coexisted with the architecture since its introduction.
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It is still possible to disable the
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.Tn APIC
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system and revert back to a 8259-compatible
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.Tn PIC .
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But the widespread use of
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.Tn MP
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systems has made this mainly a fallback option.
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.Sh SEE ALSO
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.Xr acpi 4 ,
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.Xr ichlpcib 4 ,
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.Xr mainbus 4
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.Rs
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.%A Intel Corporation
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.%T Intel 64 and IA-32 Architectures Software Developer's Manual
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.%V Volume 3A: System Programming Guide, Part 1
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.%P Chapter 10
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.%D January, 2011
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.%U http://www.intel.com/Assets/PDF/manual/253668.pdf
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.Re
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.Rs
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.%A Intel Corporation
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.%T Intel 82093AA I/O Advanced Programmable
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.%T Interrupt Controller (I/O APIC) Datasheet
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.%D May, 1996
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.%U http://www.intel.com/design/chipsets/datashts/29056601.pdf
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.Re
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.Rs
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.%A Intel Corporation
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.%T 8259A, Programmable Interrupt Controller
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.%D December, 1988
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.%U http://pdos.csail.mit.edu/6.828/2005/readings/hardware/8259A.pdf
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.Re
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.Rs
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.%A John Baldwin
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.%T PCI Interrupts for x86 Machines under FreeBSD
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.%D May 18-19, 2007
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.%O Proceedings of BSDCan 2007
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.%U http://people.freebsd.org/~jhb/papers/bsdcan/2007/article.pdf
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.Re
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.Rs
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.%A Microsoft Corporation
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.%T PCI IRQ Routing on a Multiprocessor ACPI System
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.%D December 4, 2001
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.%U http://www.microsoft.com/whdc/archive/acpi-mp.mspx
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.Re
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.Sh AUTHORS
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.An -nosplit
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Authors of the
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.Nx
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implementation of the Intel APIC Architecture include
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.An Andrew Doran ,
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.An Bill Sommerfeld ,
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.An Frank van der Linden ,
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and
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.An Stefan Grefen ,
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among others.
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The older 8259
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.Tn PIC
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implementation is based on the work of
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.An William Jolitz .
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