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92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/* $NetBSD: fpu.h,v 1.10 2013/12/01 01:05:16 christos Exp $ */
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#ifndef _AMD64_FPU_H_
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#define _AMD64_FPU_H_
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/*
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* NetBSD/amd64 only uses the extended save/restore format used
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* by fxsave/fsrestore, to always deal with the SSE registers,
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* which are part of the ABI to pass floating point values.
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*
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* The memory used for the 'fsave' instruction must be 16 byte aligned,
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* but the definition here isn't aligned to avoid padding elsewhere.
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*/
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struct fxsave64 {
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uint16_t fx_fcw; /* 0: FPU control word */
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uint16_t fx_fsw; /* 2: FPU status word */
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uint8_t fx_ftw; /* 4: Abridged FPU tag word */
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uint8_t fx_reserved1; /* 5: */
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uint16_t fx_fop; /* 6: Low 11 bits are FPU opcode */
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uint64_t fx_rip; /* 8: Address of faulting instruction */
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uint64_t fx_rdp; /* 16: Data address associated with fault */
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uint32_t fx_mxcsr; /* 24: SIMD control & status */
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uint32_t fx_mxcsr_mask; /* 28: */
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uint64_t fx_st[8][2]; /* 32: 8 normal FP regs (80 bit) */
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uint64_t fx_xmm[16][2]; /* 160: 16 SSE2 registers */
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uint8_t fx_reserved2[48]; /* 416: */
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uint8_t fx_available[48]; /* 464: could be used by kernel */
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};
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__CTASSERT(sizeof (struct fxsave64) == 512);
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struct savefpu {
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struct fxsave64 fp_fxsave; /* see above */
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};
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struct savefpu_i387 {
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uint16_t fp_ex_sw; /* saved status from last exception */
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uint16_t fp_ex_tw; /* saved tag from last exception */
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};
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/*
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* The i387 defaults to Intel extended precision mode and round to nearest,
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* with all exceptions masked.
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*/
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#define __INITIAL_NPXCW__ 0x037f
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#define __INITIAL_MXCSR__ 0x1f80
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#define __INITIAL_MXCSR_MASK__ 0xffbf
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/* Modern NetBSD uses the default control word.. */
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#define __NetBSD_NPXCW__ 0x037f
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/* NetBSD before 6.99.26 forced IEEE double precision. */
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#define __NetBSD_COMPAT_NPXCW__ 0x127f
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/* Linux just uses the default control word. */
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#define __Linux_NPXCW__ 0x037f
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/*
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* The standard control word from finit is 0x37F, giving:
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* Now we want:
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* affine mode (if we decide to support 287's)
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* round to nearest
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* 53-bit precision
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* all exceptions masked.
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*
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* 64-bit precision often gives bad results with high level languages
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* because it makes the results of calculations depend on whether
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* intermediate values are stored in memory or in FPU registers.
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*/
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#ifdef _KERNEL
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/*
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* XXX
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*/
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struct trapframe;
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struct cpu_info;
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void fpuinit(struct cpu_info *);
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void fpudrop(void);
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void fpusave(struct lwp *);
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void fpudiscard(struct lwp *);
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void fputrap(struct trapframe *);
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void fpusave_lwp(struct lwp *, bool);
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void fpusave_cpu(bool);
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#endif
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#endif /* _AMD64_FPU_H_ */
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