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103 lines
3.4 KiB
C
103 lines
3.4 KiB
C
/*-
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* Copyright (c) 2010 Genetec Corporation. All rights reserved.
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* Written by Hiroyuki Bessho for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS
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* OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Watchdog register definitions for Freescale i.MX31 and i.MX51
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*
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* MCIMX31 and MCIMX31L Application Processors
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* Reference Manual
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* MCIMC31RM
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* Rev. 2.3
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* 1/2007
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*
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* MCIMX51 Multimedia Applications Processor
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* Reference Manual
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* MCIMX51RM
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* Rev. 1
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* 2/2010
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*/
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#ifndef IMXWDOGREG_H
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#define IMXWDOGREG_H
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#ifdef _LOCORE
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#ifndef __BIT
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#define __BIT(n) (1<<(n))
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#endif
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#ifndef __BITS
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#define __BITS(hi,lo) (((1<<((hi)+1))-1) & ~((1<<((lo))-1))
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#endif
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#else
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#include <sys/cdefs.h>
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#endif
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#define IMX_WDOG_WCR 0x0000 /* Watchdog Control Register */
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#define WCR_WDZST __BIT(0) /* watchdog low power */
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#define WCR_WDBG __BIT(1) /* watchdog debug enable */
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#define WCR_WDE __BIT(2) /* watchdog enable */
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#define WCR_WDT __BIT(3) /* timeout assertion */
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#define WCR_SRS __BIT(4) /* software reset signal */
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#define WCR_WDA __BIT(5) /* ipp_wdog* assertion */
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#define WCR_WDW __BIT(7) /* disable for wait */
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#define WCR_WT_SHIFT 8
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#define WCR_WT_LEN 8
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#define WCR_WT_MASK __BIT(WCR_WT_SHIFT+WCR_WT_LEN-1, WCR_WT_SHIFT)
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/* watchdog timeout
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0=0.5sec 0xff=128sec */
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#define IMX_WDOG_WSR 0x0002 /* Watchdog Service Register */
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#define WSR_MAGIC1 0x5555 /* 1st word of service sequence */
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#define WSR_MAGIC2 0xaaaa /* 2nd word of service sequence */
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#define IMX_WDOG_WRSR 0x0004 /* Watchdog Reset Status Register */
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#define WRSR_SFTW __BIT(0) /* reset is the result of a
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* software reset */
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#define WRSR_TOUT __BIT(1) /* reset is the result of a
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* WDOG timeout */
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/* only for i.MX31 */
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#define WRSR_CMON __BIT(2)
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#define WRSR_EXT __BIT(3)
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#define WRSR_PWR __BIT(4)
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#define WRSR_JRST __BIT(5)
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/* only for i.MX51 */
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#define IMX_WDOG_WICR 0x0006 /* Watchdog Interrupt Control Register */
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#define WICR_WICT_LEN 8
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#define WICR_WICT_MASK __BITS(WICT_LEN-1,0) /* interrupt count timeout */
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#define WICR_WTIS __BIT(14) /* interrupt status [w1c] */
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#define WICR_WIE __BIT(15) /* interrupt enable */
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/* only for i.MX51 */
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#define IMX_WDOG_WMCR 0x0008
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#define WMCR_PDE __BIT(0) /* power down enable */
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#endif
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