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64 lines
2.5 KiB
C
64 lines
2.5 KiB
C
/* $NetBSD: aupcivar.h,v 1.3 2011/04/04 20:37:51 dyoung Exp $ */
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/*-
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* Copyright (c) 2006 Itronix Inc.
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* All rights reserved.
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*
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* Written by Garrett D'Amore for Itronix Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of Itronix Inc. may not be used to endorse
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* or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _MIPS_ALCHEMY_DEV_AUPCIVAR_H
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#define _MIPS_ALCHEMY_DEV_AUPCIVAR_H
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#include <dev/pci/pcivar.h>
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/*
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* PCI configuration space encompasses all 32-bits.
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*
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* PCI memory space encompasses all 32-bits, excepting that portion of
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* the address space that is decoded by the Alchemy core for accesses
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* to host memory. (That range is determined dynamically.)
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*
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* PCI I/O address range. We want to start offset from zero to avoid
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* potential problems with devices. These addresses do not
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* participate on the Alchemy system bus, hence we can choose any
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* range we like. 16 MB is plenty.
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*/
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#define AUPCI_IO_START 0x1000000
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#define AUPCI_IO_END 0x1FFFFFF
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/*
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* Machdep code must implement this. Stores an IRQ number in
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* pci_intr_handle_t. See pci_intr_map(9) for more detail. Returns 0
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* on success, non-zero on failure.
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*/
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int aupci_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
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#endif /* _MIPS_ALCHEMY_DEV_AUPCIVAR_H */
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