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325 lines
7.8 KiB
C
325 lines
7.8 KiB
C
/* $NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: cpu.c,v 1.32 2011/06/21 04:21:16 matt Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/evcnt.h>
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#include <sys/cpu.h>
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#include <uvm/uvm_extern.h>
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#include <prop/proplib.h>
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#include <powerpc/ibm4xx/cpu.h>
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#include <powerpc/ibm4xx/dev/plbvar.h>
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struct cputab {
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u_int version;
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u_int mask;
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const char *name;
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struct cache_info ci;
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};
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static const struct cputab models[] = {
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{
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.version = PVR_401A1,
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.mask = 0xffff0000,
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.name = "401A1",
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.ci = {
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.dcache_size = 1024,
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.dcache_line_size = 16,
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.icache_size = 2848,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401B2,
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.mask = 0xffff0000,
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.name = "401B21",
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.ci = {
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.dcache_size = 8192,
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.dcache_line_size = 16,
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.icache_size = 16384,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401C2,
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.mask = 0xffff0000,
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.name = "401C2",
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.ci = {
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.dcache_size = 8192,
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.dcache_line_size = 16,
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.icache_size = 0,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401D2,
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.mask = 0xffff0000,
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.name = "401D2",
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.ci = {
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.dcache_size = 2848,
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.dcache_line_size = 16,
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.icache_size = 4096,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401E2,
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.mask = 0xffff0000,
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.name = "401E2",
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.ci = {
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.dcache_size = 0,
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.dcache_line_size = 16,
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.icache_size = 0,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401F2,
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.mask = 0xffff0000,
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.name = "401F2",
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.ci = {
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.dcache_size = 2048,
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.dcache_line_size = 16,
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.icache_size = 2848,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_401G2,
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.mask = 0xffff0000,
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.name = "401G2",
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.ci = {
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.dcache_size = 2848,
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.dcache_line_size = 16,
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.icache_size = 8192,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_403,
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.mask = 0xffff0000,
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.name = "403",
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.ci = {
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.dcache_size = 8192,
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.dcache_line_size = 16,
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.icache_size = 16384,
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.icache_line_size = 16,
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}
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}, {
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.version = PVR_405GP,
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.mask = 0xffff0000,
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.name = "405GP",
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.ci = {
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.dcache_size = 8192,
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.dcache_line_size = 32,
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.icache_size = 8192,
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.icache_line_size = 32,
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}
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}, {
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.version = PVR_405GPR,
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.mask = 0xffff0000,
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.name = "405GPr",
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.ci = {
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.dcache_size = 16384,
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.dcache_line_size = 32,
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.icache_size = 16384,
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.icache_line_size = 32,
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}
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}, {
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.version = PVR_405D5X1,
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.mask = 0xfffff000,
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.name = "Xilinx Virtex II Pro",
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.ci = {
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.dcache_size = 16384,
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.dcache_line_size = 32,
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.icache_size = 16384,
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.icache_line_size = 32,
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}
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}, {
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.version = PVR_405D5X2,
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.mask = 0xfffff000,
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.name = "Xilinx Virtex 4 FX",
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.ci = {
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.dcache_size = 16384,
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.dcache_line_size = 32,
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.icache_size = 16384,
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.icache_line_size = 32,
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}
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}, {
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.version = PVR_405EX,
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.mask = 0xffff0000,
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.name = "405EX",
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.ci = {
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.dcache_size = 16384,
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.dcache_line_size = 32,
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.icache_size = 16384,
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.icache_line_size = 32,
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}
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}, {
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.version = 0,
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.mask = 0,
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.name = NULL,
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.ci = {
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/*
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* Unknown CPU type. For safety we'll specify a
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* cache with a 4-byte line size. That way cache
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* flush routines won't miss any lines.
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*/
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.dcache_line_size = 4,
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.icache_line_size = 4,
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},
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},
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};
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static int cpumatch(device_t, cfdata_t, void *);
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static void cpuattach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(cpu, 0, cpumatch, cpuattach, NULL, NULL);
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int ncpus;
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struct cpu_info cpu_info[1] = {
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{
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/* XXX add more ci_ev_* as we teach 4xx about them */
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.ci_ev_clock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
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NULL, "cpu0", "clock"),
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.ci_ev_statclock = EVCNT_INITIALIZER(EVCNT_TYPE_INTR,
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NULL, "cpu0", "stat clock"),
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.ci_curlwp = &lwp0,
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}
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};
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char cpu_model[80];
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bool cpufound;
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static int
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cpumatch(device_t parent, cfdata_t cf, void *aux)
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{
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struct plb_attach_args *paa = aux;
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/* make sure that we're looking for a CPU */
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if (strcmp(paa->plb_name, cf->cf_name) != 0)
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return (0);
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return !cpufound;
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}
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static void
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cpuattach(device_t parent, device_t self, void *aux)
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{
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struct cpu_info * const ci = curcpu();
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const struct cputab *cp;
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u_int processor_freq;
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prop_number_t freq;
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freq = prop_dictionary_get(board_properties, "processor-frequency");
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KASSERT(freq != NULL);
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processor_freq = (unsigned int) prop_number_integer_value(freq);
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cpufound = true;
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ncpus++;
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const u_int pvr = mfpvr();
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for (cp = models; cp->name != NULL; cp++) {
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if ((pvr & cp->mask) == cp->version) {
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strcpy(cpu_model, cp->name);
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break;
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}
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}
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if (__predict_false(cp->name == NULL))
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sprintf(cpu_model, "Version 0x%x", pvr);
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aprint_normal(": %uMHz %s (PVR 0x%x)\n",
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(processor_freq + 500000) / 1000000,
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(cp->name != NULL ? cpu_model : "unknown model"),
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pvr);
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cpu_probe_cache();
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/* We would crash later on anyway so just make the reason obvious */
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if (ci->ci_ci.icache_size == 0 && ci->ci_ci.dcache_size == 0)
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panic("%s: %s: could not detect cache size",
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__func__, device_xname(self));
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aprint_normal_dev(self, "%uKB/%uB L1 instruction cache\n",
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ci->ci_ci.icache_size / 1024, ci->ci_ci.icache_line_size);
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aprint_normal_dev(self, "%uKB/%uB L1 data cache\n",
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ci->ci_ci.dcache_size / 1024, ci->ci_ci.dcache_line_size);
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}
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/*
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* This routine must be explicitly called to initialize the
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* CPU cache information so cache flushe and memcpy operation
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* work.
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*/
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void
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cpu_probe_cache(void)
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{
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struct cpu_info * const ci = curcpu();
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const struct cputab *cp = models;
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const u_int pvr = mfpvr();
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for (cp = models; cp->name != NULL; cp++) {
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if ((pvr & cp->mask) == cp->version)
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break;
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}
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/*
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* Copy the cache from the cputab into cpu_info.
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*/
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ci->ci_ci = cp->ci;
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}
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/*
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* These small routines may have to be replaced,
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* if/when we support processors other that the 604.
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*/
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void
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dcache_wbinv_page(vaddr_t va)
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{
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const size_t dcache_line_size = curcpu()->ci_ci.dcache_line_size;
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if (dcache_line_size) {
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for (size_t i = 0; i < PAGE_SIZE; i += dcache_line_size) {
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__asm volatile("dcbf %0,%1" : : "b" (va), "r" (i));
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}
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__asm volatile("sync;isync" : : );
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}
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}
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