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ppc4xx: Setup HICB on Io64

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The FPGA High-Speed Interconnect Bus (HICB) is now setup by u-boot.

Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Dirk Eibach 2012-01-02 11:02:46 +01:00 committed by Stefan Roese
parent 9a420986cc
commit 06b174124e
2 changed files with 20 additions and 1 deletions
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16
board/gdsys/405ex/io64.c
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@ -249,6 +249,7 @@ int last_stage_init(void)
char str_serdes[] = "Start SERDES blocks"; char str_serdes[] = "Start SERDES blocks";
char str_channels[] = "Start FPGA channels"; char str_channels[] = "Start FPGA channels";
char str_locks[] = "Verify SERDES locks"; char str_locks[] = "Verify SERDES locks";
char str_hicb[] = "Verify HICB status";
char str_status[] = "Verify PHY status -"; char str_status[] = "Verify PHY status -";
char slash[] = "\\|/-\\|/-"; char slash[] = "\\|/-\\|/-";
@ -312,6 +313,21 @@ int last_stage_init(void)
} }
blank_string(strlen(str_locks)); blank_string(strlen(str_locks));
/* verify hicb_status */
puts(str_hicb);
for (fpga = 0; fpga < 2; ++fpga) {
u16 *ch0_hicb_status_int = &(fpga ? fpga1 : fpga0)->ch0_hicb_status_int;
for (k = 0; k < 32; ++k) {
u16 status = in_le16(ch0_hicb_status_int + 4*k);
if (status)
printf("fpga %d hicb %d: hicb status %04x\n",
fpga, k, status);
/* reset events */
out_le16(ch0_hicb_status_int + 4*k, status);
}
}
blank_string(strlen(str_hicb));
/* verify phy status */ /* verify phy status */
puts(str_status); puts(str_status);
for (k = 0; k < 32; ++k) { for (k = 0; k < 32; ++k) {

5
include/gdsys_fpga.h
View File

@ -82,7 +82,10 @@ typedef struct ihs_fpga {
u16 reserved_1[502]; /* 0x0014 */ u16 reserved_1[502]; /* 0x0014 */
u16 ch0_status_int; /* 0x0400 */ u16 ch0_status_int; /* 0x0400 */
u16 ch0_config_int; /* 0x0402 */ u16 ch0_config_int; /* 0x0402 */
u16 reserved_2[7677]; /* 0x0404 */ u16 reserved_2[126]; /* 0x0404 */
u16 ch0_hicb_status_int;/* 0x0500 */
u16 ch0_hicb_config_int;/* 0x0502 */
u16 reserved_3[7549]; /* 0x0504 */
u16 reflection_high; /* 0x3ffe */ u16 reflection_high; /* 0x3ffe */
} ihs_fpga_t; } ihs_fpga_t;
#endif #endif