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powerpc/mpc8xxx: Fix DDR 3-way interleaving

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Should check if interleaving is enabled before using interleaving mode.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
York Sun 2013-03-25 07:33:20 +00:00 committed by Andy Fleming
parent 054dfd9b9d
commit 0a7c5353a4
1 changed files with 11 additions and 8 deletions
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19
arch/powerpc/cpu/mpc8xxx/ddr/main.c
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@ -541,14 +541,17 @@ phys_size_t fsl_ddr_sdram(void)
total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0); total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
/* setup 3-way interleaving before enabling DDRC */ /* setup 3-way interleaving before enabling DDRC */
switch (info.memctl_opts[0].memctl_interleaving_mode) { if (info.memctl_opts[0].memctl_interleaving) {
case FSL_DDR_3WAY_1KB_INTERLEAVING: switch (info.memctl_opts[0].memctl_interleaving_mode) {
case FSL_DDR_3WAY_4KB_INTERLEAVING: case FSL_DDR_3WAY_1KB_INTERLEAVING:
case FSL_DDR_3WAY_8KB_INTERLEAVING: case FSL_DDR_3WAY_4KB_INTERLEAVING:
fsl_ddr_set_intl3r(info.memctl_opts[0].memctl_interleaving_mode); case FSL_DDR_3WAY_8KB_INTERLEAVING:
break; fsl_ddr_set_intl3r(
default: info.memctl_opts[0].memctl_interleaving_mode);
break; break;
default:
break;
}
} }
/* Program configuration registers. */ /* Program configuration registers. */