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Cache update and added CFG_UNIFY_CACHE

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Enabled cache in cpu_init_f() for faster flash to mem allocation. Updated cache handling in start.S. Applied cache invalidate in fec_send() and fec_recv(). Added CFG_UNIFY_CACHE for CF V3 only.

Signed-off-by: TsiChung <tcliew@Goku.(none)>
This commit is contained in:
TsiChung 2007-07-10 15:45:43 -05:00 committed by John Rigby
parent 52b017604a
commit 0dca874db6
4 changed files with 29 additions and 38 deletions
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3
cpu/mcf532x/cpu_init.c
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@ -113,6 +113,8 @@ void cpu_init_f(void)
fbcs->cscr5 = CFG_CS5_CTRL; fbcs->cscr5 = CFG_CS5_CTRL;
fbcs->csmr5 = CFG_CS5_MASK; fbcs->csmr5 = CFG_CS5_MASK;
#endif #endif
icache_enable();
} }
/* /*
@ -120,6 +122,5 @@ void cpu_init_f(void)
*/ */
int cpu_init_r(void) int cpu_init_r(void)
{ {
icache_enable();
return (0); return (0);
} }

12
cpu/mcf532x/start.S
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@ -270,8 +270,6 @@ icache_enable:
movec %d0, %CACR /* Invalidate cache */ movec %d0, %CACR /* Invalidate cache */
move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */ movec %d0, %ACR0 /* Enable cache */
move.l #(CFG_CS0_BASE + 0x0000), %d0 /* Setup cache mask */
movec %d0, %ACR1 /* Enable cache */
move.l #0x80000200, %d0 /* Setup cache mask */ move.l #0x80000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */ movec %d0, %CACR /* Enable cache */
@ -284,11 +282,11 @@ icache_enable:
.globl icache_disable .globl icache_disable
icache_disable: icache_disable:
move.l #0x00000100, %d0 /* Setup cache mask */ move.l #0x01000000, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */ movec %d0, %CACR /* Disable cache */
clr.l %d0 /* Setup cache mask */ clr.l %d0 /* Setup cache mask */
movec %d0, %ACR0 /* Enable cache */ movec %d0, %ACR0
movec %d0, %ACR1 /* Enable cache */ movec %d0, %ACR1
move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
moveq #0, %d0 moveq #0, %d0
@ -303,7 +301,7 @@ icache_status:
.globl icache_invalid .globl icache_invalid
icache_invalid: icache_invalid:
move.l #0x01000000, %d0 /* Setup cache mask */ move.l #0x81000200, %d0 /* Setup cache mask */
movec %d0, %CACR /* Enable cache */ movec %d0, %CACR /* Enable cache */
rts rts

26
drivers/net/mcffec.c
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@ -150,23 +150,15 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
* Wait for ready * Wait for ready
*/ */
j = 0; j = 0;
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid();
#endif
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) { (j < MCFFEC_TOUT_LOOP)) {
udelay(1); udelay(1);
j++; j++;
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid();
#endif
} }
if (j >= MCFFEC_TOUT_LOOP) { if (j >= MCFFEC_TOUT_LOOP) {
printf("TX not ready\n"); printf("TX not ready\n");
} }
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid();
#endif
info->txbd[info->txIdx].cbd_bufaddr = (uint) packet; info->txbd[info->txIdx].cbd_bufaddr = (uint) packet;
info->txbd[info->txIdx].cbd_datlen = length; info->txbd[info->txIdx].cbd_datlen = length;
info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST; info->txbd[info->txIdx].cbd_sc |= BD_ENET_TX_RDY_LST;
@ -174,21 +166,19 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
/* Activate transmit Buffer Descriptor polling */ /* Activate transmit Buffer Descriptor polling */
fecp->tdar = 0x01000000; /* Descriptor polling active */ fecp->tdar = 0x01000000; /* Descriptor polling active */
j = 0; #ifdef CFG_UNIFY_CACHE
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid(); icache_invalid();
#endif #endif
j = 0;
while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) && while ((info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_READY) &&
(j < MCFFEC_TOUT_LOOP)) { (j < MCFFEC_TOUT_LOOP)) {
udelay(1); udelay(1);
j++; j++;
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid();
#endif
} }
if (j >= MCFFEC_TOUT_LOOP) { if (j >= MCFFEC_TOUT_LOOP) {
printf("TX timeout\n"); printf("TX timeout\n");
} }
#ifdef ET_DEBUG #ifdef ET_DEBUG
printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n", printf("%s[%d] %s: cycles: %d status: %x retry cnt: %d\n",
__FILE__, __LINE__, __FUNCTION__, j, __FILE__, __LINE__, __FUNCTION__, j,
@ -196,10 +186,7 @@ int fec_send(struct eth_device *dev, volatile void *packet, int length)
(info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2); (info->txbd[info->txIdx].cbd_sc & 0x003C) >> 2);
#endif #endif
/* return only status bits */ ; /* return only status bits */
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
icache_invalid();
#endif
rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); rc = (info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS);
info->txIdx = (info->txIdx + 1) % TX_BUF_CNT; info->txIdx = (info->txIdx + 1) % TX_BUF_CNT;
@ -213,6 +200,9 @@ int fec_recv(struct eth_device *dev)
int length; int length;
for (;;) { for (;;) {
#ifdef CFG_UNIFY_CACHE
icache_invalid();
#endif
/* section 16.9.23.2 */ /* section 16.9.23.2 */
if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { if (info->rxbd[info->rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
length = -1; length = -1;

26
include/configs/M5329EVB.h
View File

@ -47,18 +47,20 @@
#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_CACHE | \ CFG_CMD_CACHE | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_ELF | \ CFG_CMD_ELF | \
CFG_CMD_FLASH | \ CFG_CMD_FLASH | \
(CFG_CMD_LOADB | CFG_CMD_LOADS) | \ (CFG_CMD_LOADB | CFG_CMD_LOADS) | \
CFG_CMD_MEMORY | \ CFG_CMD_MEMORY | \
CFG_CMD_MISC | \ CFG_CMD_MISC | \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_NET | \ CFG_CMD_NET | \
CFG_CMD_PING | \ CFG_CMD_PING | \
CFG_CMD_REGINFO \ CFG_CMD_REGINFO \
) )
#define CFG_UNIFY_CACHE
#define CONFIG_MCFFEC #define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC #ifdef CONFIG_MCFFEC