mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-10 12:39:22 -04:00
powerpc/83xx: add kmcoge5ne board support
This board is a MPC8360 board. Two flashes are present a NOR flash were u-boot and the u-boot environment is stored and a NAND flash for the application code. This board has 512MB SDRAM. Additionaly we introduce a common km8360.h file and convert kmeter1 to use this. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> Signed-off-by: Christian Herzig <christian.herzig@keymile.com> cc: Kim Phillips <kim.phillips@freescale.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Gerlando Falauto <gerlando.falauto@keymile.com> cc: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Holger Brunck
Kim Phillips
parent
cf73639d32
commit
0f2b721c80
@ -66,6 +66,10 @@ Oliver Brown <obrown@adventnetworks.com>
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gw8260 MPC8260
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gw8260 MPC8260
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Holger Brunck <holger.brunck@keymile.com>
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kmcoge5ne MPC8360
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Cyril Chemparathy <cyril@ti.com>
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Cyril Chemparathy <cyril@ti.com>
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tnetv107x_evm tnetv107x
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tnetv107x_evm tnetv107x
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@ -32,7 +32,7 @@
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* port pin dir open_drain assign */
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/* port pin dir open_drain assign */
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#if defined(CONFIG_KMETER1)
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#if defined(CONFIG_MPC8360)
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/* MDIO */
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/* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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{0, 2, 1, 0, 1}, /* MDC */
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@ -606,7 +606,8 @@ MPC8360ERDK_66 powerpc mpc83xx mpc8360erdk freesca
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MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
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MPC837XEMDS powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS
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MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
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MPC837XEMDS_HOST powerpc mpc83xx mpc837xemds freescale - MPC837XEMDS:PCI
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MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
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MPC837XERDB powerpc mpc83xx mpc837xerdb freescale
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kmeter1 powerpc mpc83xx km83xx keymile
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kmcoge5ne powerpc mpc83xx km83xx keymile - km8360:KMCOGE5NE
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kmeter1 powerpc mpc83xx km83xx keymile - km8360:KMETER1
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MERGERBOX powerpc mpc83xx mergerbox matrix_vision
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MERGERBOX powerpc mpc83xx mergerbox matrix_vision
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MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
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MVBLM7 powerpc mpc83xx mvblm7 matrix_vision
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SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
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SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
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@ -54,6 +54,8 @@
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*/
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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281
include/configs/km8360.h
Normal file
281
include/configs/km8360.h
Normal file
@ -0,0 +1,281 @@
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/*
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* (C) Copyright 2012
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* Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
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* Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* KMBEC FPGA (PRIO) */
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#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
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#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
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#if defined CONFIG_KMETER1
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#define CONFIG_HOSTNAME kmeter1
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#define CONFIG_KM_BOARD_NAME "kmeter1"
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#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
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#elif defined CONFIG_KMCOGE5NE
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#define CONFIG_HOSTNAME kmcoge5ne
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#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
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#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
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#define CONFIG_CMD_NAND
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#define CONFIG_NAND_KMETER1
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
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#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
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#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
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#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
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#define MTDPARTS_DEFAULT "mtdparts=" \
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"boot:" \
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"768k(u-boot)," \
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"128k(env)," \
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"128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
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"app:" \
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"-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
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#else
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#error ("Board not supported")
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#endif
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_QE /* Has QE */
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#define CONFIG_MPC8360 /* MPC8360 CPU specific */
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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/* include common defines/options for all 83xx Keymile boards */
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#include "km/km83xx-common.h"
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/*
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* System IO Setup
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*/
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#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
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/*
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* Hardware Reset Configuration Word
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*/
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_CSB_TO_CLKIN_4X1 | \
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HRCWL_CORE_TO_CSB_2X1 | \
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HRCWL_CE_PLL_VCO_DIV_2 | \
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HRCWL_CE_TO_PLL_1X6)
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_CORE_ENABLE | \
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HRCWH_FROM_0X00000100 | \
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HRCWH_BOOTSEQ_DISABLE | \
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HRCWH_SW_WATCHDOG_DISABLE | \
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HRCWH_ROM_LOC_LOCAL_16BIT | \
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HRCWH_BIG_ENDIAN | \
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HRCWH_LALE_EARLY | \
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HRCWH_LDP_CLEAR)
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/**
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* DDR RAM settings
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*/
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#define CONFIG_SYS_DDR_SDRAM_CFG (\
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SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_SREN | \
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SDRAM_CFG_HSE)
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
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#ifdef CONFIG_KMCOGE5NE
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/**
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* KMCOGE5NE has 512 MB RAM
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*/
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#define CONFIG_SYS_DDR_CS0_CONFIG (\
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CSCONFIG_EN | \
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CSCONFIG_AP | \
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CSCONFIG_ODT_RD_ONLY_CURRENT | \
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CSCONFIG_BANK_BIT_3 | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10)
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#else
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | \
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CSCONFIG_ODT_RD_ONLY_CURRENT)
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#endif
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#define CONFIG_SYS_DDR_CLK_CNTL (\
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DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
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#define CONFIG_SYS_DDR_INTERVAL (\
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(0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
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(0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDRCDR (\
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DDRCDR_EN | \
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DDRCDR_Q_DRN)
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#define CONFIG_SYS_DDR_MODE 0x47860452
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#define CONFIG_SYS_DDR_MODE2 0x8080c000
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#define CONFIG_SYS_DDR_TIMING_0 (\
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(2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
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(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
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(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
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(0 << TIMING_CFG0_WWT_SHIFT) | \
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(0 << TIMING_CFG0_RRT_SHIFT) | \
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 (\
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(0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
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(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
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(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
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(5 << TIMING_CFG2_CPO_SHIFT) | \
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(0 << TIMING_CFG2_ADD_LAT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
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/*
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* PAXE on the local bus CS3
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*/
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#define CONFIG_SYS_PAXE_BASE 0xA0000000
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#define CONFIG_SYS_PAXE_SIZE 256
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
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#define CONFIG_SYS_BR3_PRELIM (\
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CONFIG_SYS_PAXE_BASE | \
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(1 << BR_PS_SHIFT) | \
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BR_V)
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#define CONFIG_SYS_OR3_PRELIM (\
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MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX | \
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OR_GPCM_EAD)
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#ifdef CONFIG_KMCOGE5NE
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/*
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* BFTIC3 on the local bus CS4
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*/
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#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
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#define CONFIG_SYS_BFTIC3_SIZE 256
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#define CONFIG_SYS_BR4_PRELIM (\
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CONFIG_SYS_BFTIC3_BASE |\
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(1 << BR_PS_SHIFT) | \
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BR_V)
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#define CONFIG_SYS_OR4_PRELIM (\
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MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
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OR_GPCM_CSNT | \
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OR_GPCM_ACS_DIV2 |\
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OR_GPCM_SCY_2 |\
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OR_GPCM_TRLX |\
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OR_GPCM_EAD)
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#endif
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/*
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* MMU Setup
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*/
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/* PAXE: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT5L (\
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CONFIG_SYS_PAXE_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT5U (\
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CONFIG_SYS_PAXE_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT5L (\
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CONFIG_SYS_PAXE_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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#ifdef CONFIG_KMCOGE5NE
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/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
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#define CONFIG_SYS_IBAT6L (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATL_PP_10 | \
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BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT6U (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATU_BL_256M | \
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BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT6L (\
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CONFIG_SYS_BFTIC3_BASE | \
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BATL_PP_10 | \
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BATL_CACHEINHIBIT | \
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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/* DDR/LBC SDRAM next 256M: cacheable */
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#define CONFIG_SYS_IBAT7L (\
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CONFIG_SYS_SDRAM_BASE2 |\
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BATL_PP_10 |\
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BATL_CACHEINHIBIT |\
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BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT7U (\
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CONFIG_SYS_SDRAM_BASE2 |\
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BATU_BL_256M |\
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BATU_VS |\
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BATU_VP)
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#else
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#define CONFIG_SYS_IBAT6L (0)
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#define CONFIG_SYS_IBAT6U (0)
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#define CONFIG_SYS_IBAT7L (0)
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#define CONFIG_SYS_IBAT7U (0)
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#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
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#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
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#endif
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#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
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#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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#endif /* CONFIG */
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@ -1,172 +0,0 @@
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/*
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||||||
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
|
||||||
* Dave Liu <daveliu@freescale.com>
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 Logic Product Development, Inc.
|
|
||||||
* Peter Barada <peterb@logicpd.com>
|
|
||||||
*
|
|
||||||
* Copyright (C) 2007 MontaVista Software, Inc.
|
|
||||||
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
|
||||||
*
|
|
||||||
* (C) Copyright 2008-2011
|
|
||||||
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
*/
|
|
||||||
#define CONFIG_QE /* Has QE */
|
|
||||||
#define CONFIG_MPC8360 /* MPC8360 CPU specific */
|
|
||||||
#define CONFIG_KMETER1 /* KMETER1 board specific */
|
|
||||||
#define CONFIG_HOSTNAME kmeter1
|
|
||||||
#define CONFIG_KM_BOARD_NAME "kmeter1"
|
|
||||||
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0xF0000000
|
|
||||||
#define CONFIG_KM_DEF_NETDEV \
|
|
||||||
"netdev=eth2\0" \
|
|
||||||
|
|
||||||
/* include common defines/options for all 83xx Keymile boards */
|
|
||||||
#include "km/km83xx-common.h"
|
|
||||||
|
|
||||||
#define CONFIG_MISC_INIT_R
|
|
||||||
/*
|
|
||||||
* System IO Setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Hardware Reset Configuration Word
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_HRCW_LOW (\
|
|
||||||
HRCWL_CSB_TO_CLKIN_4X1 | \
|
|
||||||
HRCWL_CORE_TO_CSB_2X1 | \
|
|
||||||
HRCWL_CE_PLL_VCO_DIV_2 | \
|
|
||||||
HRCWL_CE_TO_PLL_1X6)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HRCW_HIGH (\
|
|
||||||
HRCWH_CORE_ENABLE | \
|
|
||||||
HRCWH_FROM_0X00000100 | \
|
|
||||||
HRCWH_BOOTSEQ_DISABLE | \
|
|
||||||
HRCWH_SW_WATCHDOG_DISABLE | \
|
|
||||||
HRCWH_ROM_LOC_LOCAL_16BIT | \
|
|
||||||
HRCWH_BIG_ENDIAN | \
|
|
||||||
HRCWH_LALE_EARLY | \
|
|
||||||
HRCWH_LDP_CLEAR)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
|
|
||||||
SDRAM_CFG_SREN)
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
|
|
||||||
#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
|
|
||||||
#define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
|
|
||||||
(0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
|
|
||||||
CSCONFIG_ROW_BIT_13 | \
|
|
||||||
CSCONFIG_COL_BIT_10 | \
|
|
||||||
CSCONFIG_ODT_WR_ONLY_CURRENT)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN)
|
|
||||||
/* 0x40000001 */
|
|
||||||
#define CONFIG_SYS_DDR_MODE 0x47860452
|
|
||||||
#define CONFIG_SYS_DDR_MODE2 0x8080c000
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
|
|
||||||
(8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
|
|
||||||
(6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
|
|
||||||
(2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
|
|
||||||
(0 << TIMING_CFG0_WWT_SHIFT) | \
|
|
||||||
(0 << TIMING_CFG0_RRT_SHIFT) | \
|
|
||||||
(0 << TIMING_CFG0_WRT_SHIFT) | \
|
|
||||||
(0 << TIMING_CFG0_RWT_SHIFT))
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
|
|
||||||
(2 << TIMING_CFG1_WRTORD_SHIFT) | \
|
|
||||||
(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
|
|
||||||
(3 << TIMING_CFG1_WRREC_SHIFT) | \
|
|
||||||
(7 << TIMING_CFG1_REFREC_SHIFT) | \
|
|
||||||
(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
|
|
||||||
(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
|
|
||||||
(3 << TIMING_CFG1_PRETOACT_SHIFT))
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
|
|
||||||
(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
|
|
||||||
(2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
|
|
||||||
(2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
|
|
||||||
(4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
|
|
||||||
(0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
|
|
||||||
(5 << TIMING_CFG2_CPO_SHIFT))
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
|
||||||
|
|
||||||
/* PRIO FPGA */
|
|
||||||
#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
|
|
||||||
#define CONFIG_SYS_KMBEC_FPGA_SIZE 128
|
|
||||||
/* PAXE FPGA */
|
|
||||||
#define CONFIG_SYS_PAXE_BASE 0xA0000000
|
|
||||||
#define CONFIG_SYS_PAXE_SIZE 512
|
|
||||||
|
|
||||||
/* EEprom support */
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Local Bus Configuration & Clock Setup
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
|
|
||||||
#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
|
|
||||||
#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Local Bus Memory Controller:
|
|
||||||
*
|
|
||||||
* Bank Bus Machine PortSz Size Device
|
|
||||||
* ---- --- ------- ------ ----- ------
|
|
||||||
* 3 Local GPCM 8 bit 512MB PAXE
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PAXE on the local bus CS3
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
|
|
||||||
#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
|
|
||||||
BR_PS_8 | /* 8 bit port size */ \
|
|
||||||
BR_MS_GPCM | /* MSEL = GPCM */ \
|
|
||||||
BR_V)
|
|
||||||
#define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
|
|
||||||
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
|
||||||
OR_GPCM_SCY_2 | \
|
|
||||||
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MMU Setup
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
|
|
||||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
|
|
||||||
BATL_MEMCOHERENCE)
|
|
||||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
|
|
||||||
BATU_VS | BATU_VP)
|
|
||||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
|
|
||||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
||||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
|
||||||
#define CONFIG_SYS_IBAT6L (0)
|
|
||||||
#define CONFIG_SYS_IBAT6U (0)
|
|
||||||
#define CONFIG_SYS_IBAT7L (0)
|
|
||||||
#define CONFIG_SYS_IBAT7U (0)
|
|
||||||
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
|
|
||||||
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
|
|
||||||
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
|
|
||||||
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
Loading…
x
Reference in New Issue
Block a user