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da850: modifications for Logic PD Rev.3 AM18xx EVM

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AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
NOR to work on Rev.3 EVM. When GP0[11] is low,
the SD0 interface will not work, but NOR flash will.

Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Nagabhushana Netagunte <nagabhushana.netagunte@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Nagabhushana Netagunte 2011-09-03 22:21:04 -04:00 committed by Albert ARIBAUD
parent ba511f779a
commit 0f3d6b06ea
2 changed files with 17 additions and 0 deletions
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4
arch/arm/include/asm/arch-davinci/hardware.h
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@ -159,6 +159,10 @@ typedef volatile unsigned int * dv_reg_p;
#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44) #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00) #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38) #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c) #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40) #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)

13
board/davinci/da8xxevm/da850evm.c
View File

@ -109,6 +109,8 @@ const struct pinmux_config nand_pins[] = {
#elif defined(CONFIG_USE_NOR) #elif defined(CONFIG_USE_NOR)
/* NOR pin muxer settings */ /* NOR pin muxer settings */
const struct pinmux_config nor_pins[] = { const struct pinmux_config nor_pins[] = {
/* GP0[11] is required for NOR to work on Rev 3 EVMs */
{ pinmux(0), 8, 4 }, /* GP0[11] */
{ pinmux(5), 1, 6 }, { pinmux(5), 1, 6 },
{ pinmux(6), 1, 6 }, { pinmux(6), 1, 6 },
{ pinmux(7), 1, 0 }, { pinmux(7), 1, 0 },
@ -278,6 +280,7 @@ u32 get_board_rev(void)
int board_init(void) int board_init(void)
{ {
u32 val;
#ifndef CONFIG_USE_IRQ #ifndef CONFIG_USE_IRQ
irq_init(); irq_init();
#endif #endif
@ -325,6 +328,16 @@ int board_init(void)
if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes))) if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
return 1; return 1;
#ifdef CONFIG_USE_NOR
/* Set the GPIO direction as output */
clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
/* Set the output as low */
val = readl(GPIO_BANK0_REG_SET_ADDR);
val |= (0x01 << 11);
writel(val, GPIO_BANK0_REG_CLR_ADDR);
#endif
#ifdef CONFIG_DRIVER_TI_EMAC #ifdef CONFIG_DRIVER_TI_EMAC
if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0) if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
return 1; return 1;