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mpc5xxx/cpu_init.c: Convert to IO accessors.

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Signed-off-by: Detlev Zundel <dzu@denx.de>
This commit is contained in:
Detlev Zundel 2009-12-18 17:35:57 +01:00 committed by Wolfgang Denk
parent 18e8989062
commit 0f597bc2a8
1 changed files with 78 additions and 48 deletions
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126
cpu/mpc5xxx/cpu_init.c
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@ -1,5 +1,5 @@
/* /*
* (C) Copyright 2000-2003 * (C) Copyright 2000-2009
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -23,6 +23,7 @@
#include <common.h> #include <common.h>
#include <mpc5xxx.h> #include <mpc5xxx.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -34,6 +35,16 @@ DECLARE_GLOBAL_DATA_PTR;
*/ */
void cpu_init_f (void) void cpu_init_f (void)
{ {
volatile struct mpc5xxx_mmap_ctl *mm =
(struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
volatile struct mpc5xxx_lpb *lpb =
(struct mpc5xxx_lpb *) MPC5XXX_LPB;
volatile struct mpc5xxx_cdm *cdm =
(struct mpc5xxx_cdm *) MPC5XXX_CDM;
volatile struct mpc5xxx_gpio *gpio =
(struct mpc5xxx_gpio *) MPC5XXX_GPIO;
volatile struct mpc5xxx_xlb *xlb =
(struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
unsigned long addecr = (1 << 25); /* Boot_CS */ unsigned long addecr = (1 << 25); /* Boot_CS */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100) #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
addecr |= (1 << 22); /* SDRAM enable */ addecr |= (1 << 22); /* SDRAM enable */
@ -48,119 +59,135 @@ void cpu_init_f (void)
* Memory Controller: configure chip selects and enable them * Memory Controller: configure chip selects and enable them
*/ */
#if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE) #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
*(vu_long *)MPC5XXX_BOOTCS_START = START_REG(CONFIG_SYS_BOOTCS_START); out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
*(vu_long *)MPC5XXX_BOOTCS_STOP = STOP_REG(CONFIG_SYS_BOOTCS_START, out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
CONFIG_SYS_BOOTCS_SIZE); CONFIG_SYS_BOOTCS_SIZE));
#endif #endif
#if defined(CONFIG_SYS_BOOTCS_CFG) #if defined(CONFIG_SYS_BOOTCS_CFG)
*(vu_long *)MPC5XXX_BOOTCS_CFG = CONFIG_SYS_BOOTCS_CFG; out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE) #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_CS0_START); out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_CS0_START, CONFIG_SYS_CS0_SIZE); out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
CONFIG_SYS_CS0_SIZE));
/* CS0 and BOOT_CS cannot be enabled at once. */ /* CS0 and BOOT_CS cannot be enabled at once. */
/* addecr |= (1 << 16); */ /* addecr |= (1 << 16); */
#endif #endif
#if defined(CONFIG_SYS_CS0_CFG) #if defined(CONFIG_SYS_CS0_CFG)
*(vu_long *)MPC5XXX_CS0_CFG = CONFIG_SYS_CS0_CFG; out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE) #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
*(vu_long *)MPC5XXX_CS1_START = START_REG(CONFIG_SYS_CS1_START); out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
*(vu_long *)MPC5XXX_CS1_STOP = STOP_REG(CONFIG_SYS_CS1_START, CONFIG_SYS_CS1_SIZE); out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
CONFIG_SYS_CS1_SIZE));
addecr |= (1 << 17); addecr |= (1 << 17);
#endif #endif
#if defined(CONFIG_SYS_CS1_CFG) #if defined(CONFIG_SYS_CS1_CFG)
*(vu_long *)MPC5XXX_CS1_CFG = CONFIG_SYS_CS1_CFG; out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE) #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
*(vu_long *)MPC5XXX_CS2_START = START_REG(CONFIG_SYS_CS2_START); out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START, CONFIG_SYS_CS2_SIZE); out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
CONFIG_SYS_CS2_SIZE));
addecr |= (1 << 18); addecr |= (1 << 18);
#endif #endif
#if defined(CONFIG_SYS_CS2_CFG) #if defined(CONFIG_SYS_CS2_CFG)
*(vu_long *)MPC5XXX_CS2_CFG = CONFIG_SYS_CS2_CFG; out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE) #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
*(vu_long *)MPC5XXX_CS3_START = START_REG(CONFIG_SYS_CS3_START); out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
*(vu_long *)MPC5XXX_CS3_STOP = STOP_REG(CONFIG_SYS_CS3_START, CONFIG_SYS_CS3_SIZE); out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
CONFIG_SYS_CS3_SIZE));
addecr |= (1 << 19); addecr |= (1 << 19);
#endif #endif
#if defined(CONFIG_SYS_CS3_CFG) #if defined(CONFIG_SYS_CS3_CFG)
*(vu_long *)MPC5XXX_CS3_CFG = CONFIG_SYS_CS3_CFG; out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE) #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
*(vu_long *)MPC5XXX_CS4_START = START_REG(CONFIG_SYS_CS4_START); out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
*(vu_long *)MPC5XXX_CS4_STOP = STOP_REG(CONFIG_SYS_CS4_START, CONFIG_SYS_CS4_SIZE); out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
CONFIG_SYS_CS4_SIZE));
addecr |= (1 << 20); addecr |= (1 << 20);
#endif #endif
#if defined(CONFIG_SYS_CS4_CFG) #if defined(CONFIG_SYS_CS4_CFG)
*(vu_long *)MPC5XXX_CS4_CFG = CONFIG_SYS_CS4_CFG; out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE) #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
*(vu_long *)MPC5XXX_CS5_START = START_REG(CONFIG_SYS_CS5_START); out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
*(vu_long *)MPC5XXX_CS5_STOP = STOP_REG(CONFIG_SYS_CS5_START, CONFIG_SYS_CS5_SIZE); out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
CONFIG_SYS_CS5_SIZE));
addecr |= (1 << 21); addecr |= (1 << 21);
#endif #endif
#if defined(CONFIG_SYS_CS5_CFG) #if defined(CONFIG_SYS_CS5_CFG)
*(vu_long *)MPC5XXX_CS5_CFG = CONFIG_SYS_CS5_CFG; out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
#endif #endif
#if defined(CONFIG_MPC5200) #if defined(CONFIG_MPC5200)
addecr |= 1; addecr |= 1;
#if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE) #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
*(vu_long *)MPC5XXX_CS6_START = START_REG(CONFIG_SYS_CS6_START); out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
*(vu_long *)MPC5XXX_CS6_STOP = STOP_REG(CONFIG_SYS_CS6_START, CONFIG_SYS_CS6_SIZE); out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
CONFIG_SYS_CS6_SIZE));
addecr |= (1 << 26); addecr |= (1 << 26);
#endif #endif
#if defined(CONFIG_SYS_CS6_CFG) #if defined(CONFIG_SYS_CS6_CFG)
*(vu_long *)MPC5XXX_CS6_CFG = CONFIG_SYS_CS6_CFG; out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE) #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
*(vu_long *)MPC5XXX_CS7_START = START_REG(CONFIG_SYS_CS7_START); out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
*(vu_long *)MPC5XXX_CS7_STOP = STOP_REG(CONFIG_SYS_CS7_START, CONFIG_SYS_CS7_SIZE); out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
CONFIG_SYS_CS7_SIZE));
addecr |= (1 << 27); addecr |= (1 << 27);
#endif #endif
#if defined(CONFIG_SYS_CS7_CFG) #if defined(CONFIG_SYS_CS7_CFG)
*(vu_long *)MPC5XXX_CS7_CFG = CONFIG_SYS_CS7_CFG; out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
#endif #endif
#if defined(CONFIG_SYS_CS_BURST) #if defined(CONFIG_SYS_CS_BURST)
*(vu_long *)MPC5XXX_CS_BURST = CONFIG_SYS_CS_BURST; out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
#endif #endif
#if defined(CONFIG_SYS_CS_DEADCYCLE) #if defined(CONFIG_SYS_CS_DEADCYCLE)
*(vu_long *)MPC5XXX_CS_DEADCYCLE = CONFIG_SYS_CS_DEADCYCLE; out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
#endif #endif
#endif /* CONFIG_MPC5200 */ #endif /* CONFIG_MPC5200 */
/* Enable chip selects */ /* Enable chip selects */
*(vu_long *)MPC5XXX_ADDECR = addecr; #if defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_CS_CTRL = (1 << 24); out_be32(&mm->addecr, addecr);
#elif defined(CONFIG_MPC5200)
out_be32(&mm->ipbi_ws_ctrl, addecr);
#endif
out_be32(&lpb->cs_ctrl, (1 << 24));
/* Setup pin multiplexing */ /* Setup pin multiplexing */
#if defined(CONFIG_SYS_GPS_PORT_CONFIG) #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
*(vu_long *)MPC5XXX_GPS_PORT_CONFIG = CONFIG_SYS_GPS_PORT_CONFIG; out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
#endif #endif
#if defined(CONFIG_MPC5200) #if defined(CONFIG_MPC5200)
/* enable timebase */ /* enable timebase */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 13); setbits_be32(&xlb->config, (1 << 13));
/* Enable snooping for RAM */ /* Enable snooping for RAM */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15); setbits_be32(&xlb->config, (1 << 15));
*(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_SYS_SDRAM_BASE | 0x1d; out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
# if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) # if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
/* Motorola reports IPB should better run at 133 MHz. */ /* Motorola reports IPB should better run at 133 MHz. */
*(vu_long *)MPC5XXX_ADDECR |= 1; #if defined(CONFIG_MGT5100)
setbits_be32(&mm->addecr, 1);
#elif defined(CONFIG_MPC5200)
setbits_be32(&mm->ipbi_ws_ctrl, 1);
#endif
/* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */ /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
addecr = *(vu_long *)MPC5XXX_CDM_CFG; addecr = in_be32(&cdm->cfg);
addecr &= ~0x103; addecr &= ~0x103;
# if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2) # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
/* pci_clk_sel = 0x01 -> IPB_CLK/2 */ /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
@ -169,15 +196,15 @@ void cpu_init_f (void)
/* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */ /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
addecr |= 0x02; addecr |= 0x02;
# endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */ # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
*(vu_long *)MPC5XXX_CDM_CFG = addecr; out_be32(&cdm->cfg, addecr);
# endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */ # endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
/* Configure the XLB Arbiter */ /* Configure the XLB Arbiter */
*(vu_long *)MPC5XXX_XLBARB_MPRIEN = 0xff; out_be32(&xlb->master_pri_enable, 0xff);
*(vu_long *)MPC5XXX_XLBARB_MPRIVAL = 0x11111111; out_be32(&xlb->master_priority, 0x11111111);
# if defined(CONFIG_SYS_XLB_PIPELINING) # if defined(CONFIG_SYS_XLB_PIPELINING)
/* Enable piplining */ /* Enable piplining */
*(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31); clrbits_be32(&xlb->config, (1 << 31));
# endif # endif
#endif /* CONFIG_MPC5200 */ #endif /* CONFIG_MPC5200 */
} }
@ -187,16 +214,19 @@ void cpu_init_f (void)
*/ */
int cpu_init_r (void) int cpu_init_r (void)
{ {
volatile struct mpc5xxx_intr *intr =
(struct mpc5xxx_intr *) MPC5XXX_ICTL;
/* mask all interrupts */ /* mask all interrupts */
#if defined(CONFIG_MGT5100) #if defined(CONFIG_MGT5100)
*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xfffffc00; out_be32(&intr->per_mask, 0xfffffc00);
#elif defined(CONFIG_MPC5200) #elif defined(CONFIG_MPC5200)
*(vu_long *)MPC5XXX_ICTL_PER_MASK = 0xffffff00; out_be32(&intr->per_mask, 0xffffff00);
#endif #endif
*(vu_long *)MPC5XXX_ICTL_CRIT |= 0x0001ffff; setbits_be32(&intr->main_mask, 0x0001ffff);
*(vu_long *)MPC5XXX_ICTL_EXT &= ~0x00000f00; clrbits_be32(&intr->ctrl, 0x00000f00);
/* route critical ints to normal ints */ /* route critical ints to normal ints */
*(vu_long *)MPC5XXX_ICTL_EXT |= 0x00000001; setbits_be32(&intr->ctrl, 0x00000001);
#if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC) #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
/* load FEC microcode */ /* load FEC microcode */