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83xx, kmeter1: autodetect size of DDR II RAM
it is possible that some board variants have different DDR II RAM sizes. So we autodetect the size of the assembled RAM. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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@ -29,6 +29,8 @@
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#include "../common/common.h"
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#include "../common/common.h"
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extern void disable_addr_trans (void);
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extern void enable_addr_trans (void);
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* port pin dir open_drain assign */
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/* port pin dir open_drain assign */
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@ -111,16 +113,7 @@ int fixed_sdram(void)
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u32 ddr_size;
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u32 ddr_size;
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u32 ddr_size_log2;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1)
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return -1;
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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@ -136,6 +129,21 @@ int fixed_sdram(void)
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udelay (200);
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udelay (200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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msize = CONFIG_SYS_DDR_SIZE << 20;
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disable_addr_trans ();
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msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
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enable_addr_trans ();
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msize /= (1024 * 1024);
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if (CONFIG_SYS_DDR_SIZE != msize) {
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
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if (ddr_size & 1)
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return -1;
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
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}
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return msize;
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return msize;
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}
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}
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@ -92,8 +92,8 @@
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* Manually set up DDR parameters
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* Manually set up DDR parameters
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*/
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*/
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#define CONFIG_DDR_II
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#define CONFIG_DDR_II
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
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CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
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