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https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
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Add PPC4xx-HCU4 and HCU5 boards: HCU5 files
Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
This commit is contained in:
Niklaus Giger
Stefan Roese
parent
6e5de26c6e
commit
157cda4d0c
526
board/netstal/hcu5/hcu5.c
Normal file
526
board/netstal/hcu5/hcu5.c
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@ -0,0 +1,526 @@
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/*
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*(C) Copyright 2005-2007 Netstal Maschinen AG
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* Niklaus Giger (Niklaus.Giger@netstal.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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#include <asm/mmu.h>
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DECLARE_GLOBAL_DATA_PTR;
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void sysLedSet(u32 value);
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extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
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#define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
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mtdcr(CPR0_CFGDATA,data); } while (0)
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#define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
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data = mfdcr(CPR0_CFGDATA); } while (0)
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#define SDR0_CP440 0x0180
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/*
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* This function is run very early, out of flash, and before devices are
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* initialized. It is called by lib_ppc/board.c:board_init_f by virtue
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* of being in the init_sequence array.
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*
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* The SDRAM has been initialized already -- start.S:start called
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* init.S:init_sdram early on -- but it is not yet being used for
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* anything, not even stack. So be careful.
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*/
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int board_early_init_f(void)
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{
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u32 reg;
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#undef BOOTSTRAP_OPTION_A_ACTIVE
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#ifdef BOOTSTRAP_OPTION_A_ACTIVE
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/* Booting with Bootstrap Option A
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* First boot, with CPR0_ICFG_RLI_MASK == 0
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* no we setup varios boot strapping register,
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* then we do reset the PPC440 using a chip reset
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* Unfortunately, we cannot use this option, as Nto1 is not set
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* with Bootstrap Option A and cannot be changed later on by SW
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* There are no other possible boostrap options with a 8 bit ROM
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* See Errata (Version 1.04) CHIP_9
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*/
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u32 cpr0icfg;
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u32 dbcr;
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mfcpr0(CPR0_ICFG, cpr0icfg);
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if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) {
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mtcpr0(CPR0_MALD, 0x02000000);
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mtcpr0(CPR0_OPBD, 0x02000000);
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mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */
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mtcpr0(CPR0_PLLC, 0x40000238);
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mtcpr0(CPR0_PLLD, 0x01010414);
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mtcpr0(CPR0_PRIMAD, 0x01000000);
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mtcpr0(CPR0_PRIMBD, 0x01000000);
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mtcpr0(CPR0_SPCID, 0x03000000);
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mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
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/*
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* Initiate system reset in debug control register DBCR
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*/
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dbcr = mfspr(dbcr0);
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#define SYSTEM_RESET 0x30000000
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#define CHIP_RESET 0x20000000
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mtspr(dbcr0, dbcr | CHIP_RESET );
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}
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mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
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#endif
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mtdcr(ebccfga, xbcfg);
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mtdcr(ebccfgd, 0xb8400000);
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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/* test-only: take GPIO init from pcs440ep ???? in config file */
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out32(GPIO0_OR, 0x00000000);
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out32(GPIO0_TCR, 0x7C2FF1CF);
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out32(GPIO0_OSRL, 0x40055000);
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out32(GPIO0_OSRH, 0x00000000);
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out32(GPIO0_TSRL, 0x40055000);
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out32(GPIO0_TSRH, 0x00000400);
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out32(GPIO0_ISR1L, 0x40000000);
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out32(GPIO0_ISR1H, 0x00000000);
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out32(GPIO0_ISR2L, 0x00000000);
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out32(GPIO0_ISR2H, 0x00000000);
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out32(GPIO0_ISR3L, 0x00000000);
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out32(GPIO0_ISR3H, 0x00000000);
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out32(GPIO1_OR, 0x00000000);
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out32(GPIO1_TCR, 0xC6007FFF);
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out32(GPIO1_OSRL, 0x00140000);
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out32(GPIO1_OSRH, 0x00000000);
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out32(GPIO1_TSRL, 0x00000000);
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out32(GPIO1_TSRH, 0x00000000);
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out32(GPIO1_ISR1L, 0x05415555);
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out32(GPIO1_ISR1H, 0x40000000);
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out32(GPIO1_ISR2L, 0x00000000);
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out32(GPIO1_ISR2H, 0x00000000);
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out32(GPIO1_ISR3L, 0x00000000);
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out32(GPIO1_ISR3H, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
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mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtdcr(uic2er, 0x00000000); /* disable all */
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mtdcr(uic2cr, 0x00000000); /* all non-critical */
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mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
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mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
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mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(uic2sr, 0xffffffff); /* clear all */
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mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
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mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
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/* PCI arbiter enabled */
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mfsdr(sdr_pci0, reg);
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mtsdr(sdr_pci0, 0x80000000 | reg);
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pci_pre_init(0);
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/* setup BOOT FLASH */
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mtsdr(SDR0_CUST0, 0xC0082350);
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return 0;
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}
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#ifdef CONFIG_BOARD_PRE_INIT
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int board_pre_init (void)
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{
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return board_early_init_f ();
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}
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#endif
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enum {
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/* HW_GENERATION_HCU1 is no longer supported */
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HW_GENERATION_HCU2 = 0x10,
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HW_GENERATION_HCU3 = 0x10,
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HW_GENERATION_HCU4 = 0x20,
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HW_GENERATION_HCU5 = 0x30,
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HW_GENERATION_MCU = 0x08,
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HW_GENERATION_MCU20 = 0x0a,
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HW_GENERATION_MCU25 = 0x09,
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};
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int checkboard (void)
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{
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#define SDR0_ECID0 0x0080
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#define SDR0_ECID1 0x0081
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#define SDR0_ECID2 0x0082
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#define SDR0_ECID3 0x0083
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unsigned j;
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uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER;
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uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER;
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uint16_t generation = *boardVersReg & 0xf0;
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uint16_t index = *boardVersReg & 0x0f;
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ulong ecid0, ecid1, ecid2, ecid3;
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printf ("Netstal Maschinen AG: ");
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if (generation == HW_GENERATION_HCU3)
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printf ("HCU3: index %d", index);
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else if (generation == HW_GENERATION_HCU4)
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printf ("HCU4: index %d", index);
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else if (generation == HW_GENERATION_HCU5)
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printf ("HCU5: index %d", index);
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printf (" HW 0x%02x\n", *hwVersReg & 0xff);
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mfsdr(SDR0_ECID0, ecid0);
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mfsdr(SDR0_ECID1, ecid1);
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mfsdr(SDR0_ECID2, ecid2);
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mfsdr(SDR0_ECID3, ecid3);
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printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
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for (j=0; j < 6;j++) {
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sysLedSet(1 << j);
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udelay(200*1000);
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}
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return 0;
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}
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#define SYS_IO_ADDRESS 0xcce00000
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u32 sysLedGet(void)
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{
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return in16(SYS_IO_ADDRESS) & 0x3f;
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}
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void sysLedSet(u32 value /* value to place in LEDs */)
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{
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out16(SYS_IO_ADDRESS, value);
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}
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/*---------------------------------------------------------------------------+
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* getSerialNr
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*---------------------------------------------------------------------------*/
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static u32 getSerialNr(void)
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{
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u32 *serial = (u32 *)CFG_FLASH_BASE;
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if (*serial == 0xffffffff) {
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return get_ticks();
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}
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return *serial;
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}
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/*---------------------------------------------------------------------------+
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* misc_init_r.
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*---------------------------------------------------------------------------*/
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#define DEFAULT_ETH_ADDR "ethaddr"
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/* ethaddr for first or etha1ddr for second ethernet */
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int misc_init_r(void)
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{
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char *s = getenv(DEFAULT_ETH_ADDR);
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char *e;
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int i;
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u32 serial = getSerialNr();
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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for (i = 0; i < 6; ++i) {
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gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
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if (s)
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s = (*e) ? e + 1 : e;
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}
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if (gd->bd->bi_enetaddr[3] == 0 &&
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gd->bd->bi_enetaddr[4] == 0 &&
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gd->bd->bi_enetaddr[5] == 0) {
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char ethaddr[22];
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/* Must be in sync with CONFIG_ETHADDR */
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gd->bd->bi_enetaddr[0] = 0x00;
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gd->bd->bi_enetaddr[1] = 0x60;
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gd->bd->bi_enetaddr[2] = 0x13;
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gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
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gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
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/* byte[5].bit 0 must be zero */
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gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
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sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
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gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
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gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
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gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
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printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
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ethaddr, serial);
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setenv (DEFAULT_ETH_ADDR, ethaddr);
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}
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#ifdef CFG_ENV_IS_IN_FLASH
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CFG_MONITOR_LEN,
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0xffffffff,
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&flash_info[0]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
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&flash_info[0]);
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#endif
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/*
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* USB stuff...
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*/
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB2D0CR, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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/* To enable the USB 2.0 Device function through the UTMI interface */
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usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
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usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
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sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
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sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB2D0CR, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*clear resets*/
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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return 0;
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}
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
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int pci_pre_init(struct pci_controller *hose)
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{
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unsigned long addr;
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/*-------------------------------------------------------------------+
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* As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
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* Workaround: Disable write pipelining to DDR SDRAM by setting
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* PLB0_ACR[WRP] = 0.
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*-------------------------------------------------------------------*/
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/*-------------------------------------------------------------------+
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| Set priority for all PLB3 devices to 0.
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| Set PLB3 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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mfsdr(sdr_amp1, addr);
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mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb3_acr);
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// mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
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mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set priority for all PLB4 devices to 0.
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+-------------------------------------------------------------------*/
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mfsdr(sdr_amp0, addr);
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mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
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addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
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// mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
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mtdcr(plb4_acr, addr); /* Sequoia */
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/*-------------------------------------------------------------------+
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| Set Nebula PLB4 arbiter to fair mode.
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+-------------------------------------------------------------------*/
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/* Segment0 */
|
||||
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
|
||||
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
|
||||
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
|
||||
// addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */
|
||||
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
|
||||
|
||||
// mtdcr(plb0_acr, addr); /* Sequoia */
|
||||
mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
|
||||
|
||||
|
||||
/* Segment1 */
|
||||
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
|
||||
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
|
||||
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
|
||||
addr = (addr & ~plb1_acr_wrp_mask) ;
|
||||
// mtdcr(plb1_acr, addr); /* Sequoia */
|
||||
mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
|
||||
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_target_init
|
||||
*
|
||||
* The bootstrap configuration provides default settings for the pci
|
||||
* inbound map (PIM). But the bootstrap config choices are limited and
|
||||
* may not be sufficient for a given board.
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
|
||||
void pci_target_init(struct pci_controller *hose)
|
||||
{
|
||||
/*-------------------------------------------------------------+
|
||||
* Set up Direct MMIO registers
|
||||
*-------------------------------------------------------------*/
|
||||
/*-------------------------------------------------------------+
|
||||
| PowerPC440EPX PCI Master configuration.
|
||||
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
|
||||
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
|
||||
| 0xA0000000-0xDFFFFFFF
|
||||
| Use byte reversed out routines to handle endianess.
|
||||
| Make this region non-prefetchable.
|
||||
+-------------------------------------------------------------*/
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM0MA, 0x00000000);
|
||||
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
|
||||
/* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
|
||||
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
/* 512M + No prefetching, and enable region */
|
||||
out32r(PCIX0_PMM0MA, 0xE0000001);
|
||||
|
||||
/* PMM0 Mask/Attribute - disabled b4 setting */
|
||||
out32r(PCIX0_PMM1MA, 0x00000000);
|
||||
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
|
||||
/* PMM0 PCI Low Address */
|
||||
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
|
||||
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
|
||||
/* 512M + No prefetching, and enable region */
|
||||
out32r(PCIX0_PMM1MA, 0xE0000001);
|
||||
|
||||
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
|
||||
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
|
||||
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
|
||||
|
||||
/*------------------------------------------------------------------+
|
||||
* Set up Configuration registers
|
||||
*------------------------------------------------------------------*/
|
||||
|
||||
/* Program the board's subsystem id/vendor id */
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
|
||||
CFG_PCI_SUBSYS_VENDORID);
|
||||
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
|
||||
|
||||
/* Configure command register as bus master */
|
||||
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
|
||||
|
||||
/* 240nS PCI clock */
|
||||
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
|
||||
|
||||
/* No error reporting */
|
||||
pci_write_config_word(0, PCI_ERREN, 0);
|
||||
|
||||
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
|
||||
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* pci_master_init
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
|
||||
void pci_master_init(struct pci_controller *hose)
|
||||
{
|
||||
unsigned short temp_short;
|
||||
|
||||
/*---------------------------------------------------------------+
|
||||
| Write the PowerPC440 EP PCI Configuration regs.
|
||||
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
|
||||
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
|
||||
+--------------------------------------------------------------*/
|
||||
pci_read_config_word(0, PCI_COMMAND, &temp_short);
|
||||
pci_write_config_word(0, PCI_COMMAND,
|
||||
temp_short | PCI_COMMAND_MASTER |
|
||||
PCI_COMMAND_MEMORY);
|
||||
}
|
||||
#endif
|
||||
/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
|
||||
|
||||
/*************************************************************************
|
||||
* is_pci_host
|
||||
*
|
||||
* This routine is called to determine if a pci scan should be
|
||||
* performed. With various hardware environments (especially cPCI and
|
||||
* PPMC) it's insufficient to depend on the state of the arbiter enable
|
||||
* bit in the strap register, or generic host/adapter assumptions.
|
||||
*
|
||||
* Rather than hard-code a bad assumption in the general 440 code, the
|
||||
* 440 pci code requires the board to decide at runtime.
|
||||
*
|
||||
* Return 0 for adapter mode, non-zero for host (monarch) mode.
|
||||
*
|
||||
*
|
||||
************************************************************************/
|
||||
#if defined(CONFIG_PCI)
|
||||
int is_pci_host(struct pci_controller *hose)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
#endif /* defined(CONFIG_PCI) */
|
||||
|
||||
81
board/netstal/hcu5/init.S
Normal file
81
board/netstal/hcu5/init.S
Normal file
@ -0,0 +1,81 @@
|
||||
/*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
*
|
||||
* This table is used by the cpu boot code to setup the initial tlb
|
||||
* entries. Rather than make broad assumptions in the cpu source tree,
|
||||
* this table lets each board set things up however they like.
|
||||
*
|
||||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
|
||||
/* vxWorks needs this entry for the Machine Check interrupt, */
|
||||
/* tlbentry( 0x40000000, SZ_256M, 0, 1, AC_R|AC_W|AC_X|SA_G|SA_I ) */
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be second. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
|
||||
|
||||
/* TLB-entry for PCI Memory */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for EBC (CFG_CPLD) */
|
||||
// tlbentry( CFG_CPLD, SZ_1K, CFG_CPLD, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* CAN */
|
||||
tlbentry( CFG_CS_1, SZ_16M, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC + CPLD */
|
||||
tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
/* IMC-Fast */
|
||||
tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3 + 0x1000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for Internal Registers & OCM */
|
||||
tlbentry( CFG_PCI_BASE, SZ_16M, 0xe0000000, 0, AC_R|AC_W|AC_X|SA_I )
|
||||
|
||||
/*TLB-entry PCI registers*/
|
||||
tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
|
||||
/* TLB-entry for peripherals */
|
||||
tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* TLB for SDRAM will be added by initdram (sdram.c) */
|
||||
|
||||
tlbtab_end
|
||||
|
||||
|
||||
299
board/netstal/hcu5/sdram.c
Normal file
299
board/netstal/hcu5/sdram.c
Normal file
@ -0,0 +1,299 @@
|
||||
/*
|
||||
* (C) Copyright 2007
|
||||
* Niklaus Giger (Niklaus.Giger@netstal.com)
|
||||
* (C) Copyright 2006
|
||||
* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
|
||||
* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
|
||||
* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
|
||||
* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
|
||||
* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* define DEBUG for debug output */
|
||||
#undef DEBUG
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <ppc440.h>
|
||||
|
||||
void sysLedSet(u32 value);
|
||||
void dcbz_area(u32 start_address, u32 num_bytes);
|
||||
void dflush(void);
|
||||
|
||||
#define DDR_DCR_BASE 0x10
|
||||
#define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
|
||||
#define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
|
||||
|
||||
#define DDR0_01_INT_MASK_MASK 0x000000FF
|
||||
#define DDR0_00_INT_ACK_ALL 0x7F000000
|
||||
#define DDR0_01_INT_MASK_ALL_ON 0x000000FF
|
||||
#define DDR0_01_INT_MASK_ALL_OFF 0x00000000
|
||||
|
||||
#define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
|
||||
#define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
|
||||
#define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
|
||||
|
||||
#define DDR0_22 0x16
|
||||
/* ECC */
|
||||
#define DDR0_22_CTRL_RAW_MASK 0x03000000
|
||||
#define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
|
||||
#define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
|
||||
#define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
|
||||
#define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
|
||||
#define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
|
||||
|
||||
#ifdef CFG_ENABLE_SDRAM_CACHE
|
||||
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
|
||||
#else
|
||||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
|
||||
#endif
|
||||
|
||||
void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
|
||||
|
||||
#ifdef CONFIG_ADD_RAM_INFO
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
PPC440_SYS_INFO board_cfg;
|
||||
u32 val;
|
||||
mfsdram(DDR0_22, val);
|
||||
val &= DDR0_22_CTRL_RAW_MASK;
|
||||
switch (val) {
|
||||
case DDR0_22_CTRL_RAW_ECC_DISABLE:
|
||||
puts(" (ECC disabled");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
|
||||
puts(" (ECC check only");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_NO_ECC_RAM:
|
||||
puts(" (no ECC ram");
|
||||
break;
|
||||
case DDR0_22_CTRL_RAW_ECC_ENABLE:
|
||||
puts(" (ECC enabled");
|
||||
break;
|
||||
}
|
||||
|
||||
get_sys_info(&board_cfg);
|
||||
printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
|
||||
|
||||
mfsdram(DDR0_03, val);
|
||||
val = DDR0_03_CASLAT_DECODE(val);
|
||||
printf(", CL%d)", val);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* wait_for_dlllock.
|
||||
*--------------------------------------------------------------------*/
|
||||
static int wait_for_dlllock(void)
|
||||
{
|
||||
unsigned long val;
|
||||
int wait = 0;
|
||||
|
||||
/* -----------------------------------------------------------+
|
||||
* Wait for the DCC master delay line to finish calibration
|
||||
* ----------------------------------------------------------*/
|
||||
mtdcr(ddrcfga, DDR0_17);
|
||||
val = DDR0_17_DLLLOCKREG_UNLOCKED;
|
||||
|
||||
while (wait != 0xffff) {
|
||||
val = mfdcr(ddrcfgd);
|
||||
if ((val & DDR0_17_DLLLOCKREG_MASK) ==
|
||||
DDR0_17_DLLLOCKREG_LOCKED)
|
||||
/* dlllockreg bit on */
|
||||
return 0;
|
||||
else
|
||||
wait++;
|
||||
}
|
||||
debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
|
||||
debug("Waiting for dlllockreg bit to raise\n");
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* sdram_panic -- Panic if we cannot configure the sdram correctly
|
||||
*
|
||||
************************************************************************/
|
||||
void sdram_panic(const char *reason)
|
||||
{
|
||||
printf("\n%s: reason %s", __FUNCTION__, reason);
|
||||
sysLedSet(0xff);
|
||||
while (1) {
|
||||
}
|
||||
/* Never return */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void blank_string(int size)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
for (i=0; i<size; i++)
|
||||
putc(' ');
|
||||
for (i=0; i<size; i++)
|
||||
putc('\b');
|
||||
}
|
||||
/*---------------------------------------------------------------------------+
|
||||
* program_ecc.
|
||||
*---------------------------------------------------------------------------*/
|
||||
static void program_ecc(unsigned long start_address, unsigned long num_bytes,
|
||||
unsigned long tlb_word2_i_value)
|
||||
{
|
||||
unsigned long current_address= start_address;
|
||||
int loopi = 0;
|
||||
u32 val;
|
||||
|
||||
char str[] = "ECC generation -";
|
||||
char slash[] = "\\|/-\\|/-";
|
||||
|
||||
sync();
|
||||
eieio();
|
||||
|
||||
puts(str);
|
||||
|
||||
if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
|
||||
/* ECC bit set method for non-cached memory */
|
||||
/* This takes various seconds */
|
||||
for(current_address = 0; current_address < num_bytes;
|
||||
current_address += sizeof(u32)) {
|
||||
*(u32 *)current_address = 0;
|
||||
if ((current_address % (2 << 20)) == 0) {
|
||||
putc('\b');
|
||||
putc(slash[loopi++ % 8]);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
/* ECC bit set method for cached memory */
|
||||
/* Fast method, no noticeable delay */
|
||||
dcbz_area(start_address, num_bytes);
|
||||
dflush();
|
||||
}
|
||||
blank_string(strlen(str));
|
||||
|
||||
/* Clear error status */
|
||||
mfsdram(DDR0_00, val);
|
||||
mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
|
||||
|
||||
/* Set 'int_mask' parameter to functionnal value */
|
||||
mfsdram(DDR0_01, val);
|
||||
mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
|
||||
DDR0_01_INT_MASK_ALL_OFF));
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/***********************************************************************
|
||||
*
|
||||
* initdram -- 440EPx's DDR controller is a DENALI Core
|
||||
*
|
||||
************************************************************************/
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
#define HCU_HW_SDRAM_CONFIG_MASK 0x7
|
||||
#define INVALID_HW_CONFIG "Invalid HW-Config"
|
||||
uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER;
|
||||
unsigned int dram_size=0;
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
/* Values must be kept in sync with Excel-table <<A0001492.>> ! */
|
||||
mtsdram(DDR0_00, 0x0000190A);
|
||||
mtsdram(DDR0_01, 0x01000000);
|
||||
mtsdram(DDR0_03, 0x02030602);
|
||||
mtsdram(DDR0_04, 0x0A020200);
|
||||
mtsdram(DDR0_05, 0x02020307);
|
||||
switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
|
||||
case 0:
|
||||
dram_size = 128 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C80D); // 128MB RAM
|
||||
mtsdram(DDR0_11, 0x000FC800); // 128MB RAM
|
||||
mtsdram(DDR0_43, 0x030A0300); // 128MB RAM
|
||||
break;
|
||||
case 1:
|
||||
dram_size = 256 * 1024 * 1024 ;
|
||||
mtsdram(DDR0_06, 0x0102C812); // 256MB RAM
|
||||
mtsdram(DDR0_11, 0x0014C800); // 256MB RAM
|
||||
mtsdram(DDR0_43, 0x030A0200); // 256MB RAM
|
||||
break;
|
||||
default:
|
||||
sdram_panic(INVALID_HW_CONFIG);
|
||||
break;
|
||||
}
|
||||
dram_size -= 16 * 1024 * 1024;
|
||||
mtsdram(DDR0_07, 0x00090100);
|
||||
// TCPD=200 cycles of clock input is required to lock the DLL.
|
||||
// CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
|
||||
mtsdram(DDR0_08, 0x02C80001);
|
||||
mtsdram(DDR0_09, 0x00011D5F);
|
||||
mtsdram(DDR0_10, 0x00000100);
|
||||
mtsdram(DDR0_12, 0x00000003);
|
||||
mtsdram(DDR0_14, 0x00000000);
|
||||
mtsdram(DDR0_17, 0x1D000000);
|
||||
mtsdram(DDR0_18, 0x1D1D1D1D);
|
||||
mtsdram(DDR0_19, 0x1D1D1D1D);
|
||||
mtsdram(DDR0_20, 0x0B0B0B0B);
|
||||
mtsdram(DDR0_21, 0x0B0B0B0B);
|
||||
#define ECC_RAM 0x03267F0B
|
||||
#define NO_ECC_RAM 0x00267F0B
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
mtsdram(DDR0_22, ECC_RAM);
|
||||
#else
|
||||
mtsdram(DDR0_22, NO_ECC_RAM);
|
||||
#endif
|
||||
|
||||
mtsdram(DDR0_23, 0x00000000);
|
||||
mtsdram(DDR0_24, 0x01020001);
|
||||
mtsdram(DDR0_26, 0x2D930517);
|
||||
mtsdram(DDR0_27, 0x00008236);
|
||||
mtsdram(DDR0_28, 0x00000000);
|
||||
mtsdram(DDR0_31, 0x00000000);
|
||||
mtsdram(DDR0_42, 0x01000006);
|
||||
mtsdram(DDR0_44, 0x00000003);
|
||||
mtsdram(DDR0_02, 0x00000001);
|
||||
wait_for_dlllock();
|
||||
mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
|
||||
|
||||
/*
|
||||
* Program tlb entries for this size (dynamic)
|
||||
*/
|
||||
program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
|
||||
|
||||
/*
|
||||
* Setup 2nd TLB with same physical address but different virtual
|
||||
* address with cache enabled. This is done for fast ECC generation.
|
||||
*/
|
||||
program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* If ECC is enabled, initialize the parity bits.
|
||||
*/
|
||||
program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);
|
||||
#endif
|
||||
|
||||
return (dram_size);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user