minix/u-boot
1
0
Fork 0
mirror of https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git synced 2025-09-12 13:35:21 -04:00
Code Issues Packages Projects Releases Wiki Activity

x86: Clean up MTRR 7 right before jumping to the kernel

Browse Source 
This cleans up the rom caching optimization implemented in coreboot (and
needed throughout U-Boot runtime).

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Stefan Reinauer 2012-12-02 04:49:53 +00:00 committed by Simon Glass
parent 98568f0fa9
commit 17de114f9f
1 changed files with 18 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/x86/cpu/coreboot/coreboot.c
View File

@ -26,6 +26,8 @@
#include <asm/u-boot-x86.h> #include <asm/u-boot-x86.h>
#include <flash.h> #include <flash.h>
#include <netdev.h> #include <netdev.h>
#include <asm/msr.h>
#include <asm/cache.h>
#include <asm/arch-coreboot/tables.h> #include <asm/arch-coreboot/tables.h>
#include <asm/arch-coreboot/sysinfo.h> #include <asm/arch-coreboot/sysinfo.h>
#include <asm/arch/timestamp.h> #include <asm/arch/timestamp.h>
@ -89,3 +91,19 @@ int board_eth_init(bd_t *bis)
void setup_pcat_compatibility() void setup_pcat_compatibility()
{ {
} }
#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
int board_final_cleanup(void)
{
/* Un-cache the ROM so the kernel has one
* more MTRR available.
*/
disable_caches();
wrmsrl(MTRRphysBase_MSR(7), 0);
wrmsrl(MTRRphysMask_MSR(7), 0);
enable_caches();
return 0;
}