mirror of
https://github.com/Stichting-MINIX-Research-Foundation/u-boot.git
synced 2025-09-10 12:39:22 -04:00
ppc4xx: Beautify configuration files for Sequoia and Korat boards
Signed-off-by: Larry Johnson <lrj@acm.org>
This commit is contained in:
Larry Johnson
Stefan Roese
parent
5db6138565
commit
214398d9cb
@ -25,15 +25,15 @@
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* MA 02111-1307 USA
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*/
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/************************************************************************
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/*
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* korat.h - configuration for Korat board
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***********************************************************************/
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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/*
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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*/
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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#define CONFIG_4xx 1 /* ... PPC4xx family */
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#define CONFIG_SYS_CLK_FREQ 33333333
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@ -41,21 +41,21 @@
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*-----------------------------------------------------------------------
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/*
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* Manufacturer's information serial EEPROM parameters
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*----------------------------------------------------------------------*/
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*/
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#define MAN_DATA_EEPROM_ADDR 0x53 /* EEPROM I2C address */
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#define MAN_SERIAL_NO_FIELD 2
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#define MAN_SERIAL_NO_LENGTH 13
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#define MAN_MAC_ADDR_FIELD 3
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#define MAN_MAC_ADDR_LENGTH 17
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* Base addresses -- Note these are effective addresses where the actual
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* resources get mapped (not physical addresses).
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*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
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@ -77,9 +77,9 @@
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#define CFG_USB_HOST 0xe0000400
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#define CFG_CPLD_BASE 0xc0000000
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/*-----------------------------------------------------------------------
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/*
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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*/
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/* 440EPx has 16KB of internal SRAM, so no need for D-Cache */
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#undef CFG_INIT_RAM_DCACHE
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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@ -88,9 +88,9 @@
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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/*
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* Serial Port
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*----------------------------------------------------------------------*/
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*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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@ -100,14 +100,14 @@
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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/*
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* Environment
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*----------------------------------------------------------------------*/
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*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
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/*-----------------------------------------------------------------------
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/*
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* FLASH related
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*----------------------------------------------------------------------*/
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*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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@ -133,9 +133,9 @@
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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/*-----------------------------------------------------------------------
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/*
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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*/
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#define CFG_MBYTES_SDRAM (512) /* 512 MiB TODO: remove */
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
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@ -145,9 +145,9 @@
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#define CONFIG_PROG_SDRAM_TLB
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#define CFG_DRAM_TEST
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/*-----------------------------------------------------------------------
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/*
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* I2C
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*----------------------------------------------------------------------*/
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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@ -220,8 +220,8 @@
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
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/* buffers & descriptors */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 3
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@ -292,9 +292,9 @@
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#define CONFIG_SUPPORT_VFAT
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/*-----------------------------------------------------------------------
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/*
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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@ -302,7 +302,8 @@
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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/* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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@ -320,16 +321,16 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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/*
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* PCI stuff
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*----------------------------------------------------------------------*/
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
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/* CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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@ -338,15 +339,15 @@
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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* For booting Linux, the board info and command line data have to be in the
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* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
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* during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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/*
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* External Bus Controller (EBC) Setup
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*----------------------------------------------------------------------*/
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*/
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/* Memory Bank 0 (NOR-FLASH) initialization */
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#define CFG_EBC_PB0AP 0x04017300
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@ -360,7 +361,7 @@
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#define CFG_EBC_PB2AP 0x04017300
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#define CFG_EBC_PB2CR (CFG_CPLD_BASE | 0x00038000)
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/*-----------------------------------------------------------------------
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/*
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* GPIO Setup
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*
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* Korat GPIO usage:
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@ -423,7 +424,7 @@
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* . . . . .
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* . . . . .
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* GPIO63 xxxx x x (reserved for trace port)
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*----------------------------------------------------------------------*/
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*/
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#define CFG_GPIO_ATMEGA_SS_ 13
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#define CFG_GPIO_PHY0_FIBER_SEL 27
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@ -435,7 +436,7 @@
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#define CFG_GPIO_PHY0_EN 45
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#define CFG_GPIO_PHY1_EN 46
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/*-----------------------------------------------------------------------
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/*
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* PPC440 GPIO Configuration
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*/
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#define CFG_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
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@ -523,4 +524,5 @@
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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#endif /* __CONFIG_H */
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@ -22,15 +22,15 @@
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* MA 02111-1307 USA
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*/
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/************************************************************************
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/*
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* sequoia.h - configuration for Sequoia & Rainier boards
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***********************************************************************/
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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/*
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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*/
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/* This config file is used for Sequoia (440EPx) and Rainier (440GRx) */
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#ifndef CONFIG_RAINIER
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#define CONFIG_440EPX 1 /* Specific PPC440EPx */
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@ -54,12 +54,12 @@
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
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#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
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/*
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* Base addresses -- Note these are effective addresses where the actual
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* resources get mapped (not physical addresses).
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*/
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#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kiB for Monitor */
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#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kiB for malloc() */
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#define CFG_TLB_FOR_BOOT_FLASH 0x0003
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#define CFG_BOOT_BASE_ADDR 0xf0000000
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@ -83,9 +83,9 @@
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#define CFG_USB_HOST 0xe0000400
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#define CFG_BCSR_BASE 0xc0000000
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/*-----------------------------------------------------------------------
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/*
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* Initial RAM & stack pointer
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*----------------------------------------------------------------------*/
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*/
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/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
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#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */
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#define CFG_INIT_RAM_END (4 << 10)
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@ -93,9 +93,9 @@
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
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/*-----------------------------------------------------------------------
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/*
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* Serial Port
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*----------------------------------------------------------------------*/
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*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SERIAL_MULTI 1
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@ -105,19 +105,19 @@
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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/*-----------------------------------------------------------------------
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/*
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* Environment
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*----------------------------------------------------------------------*/
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*/
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environ vars */
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#else
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
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#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environ vars */
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#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
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#endif
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/*-----------------------------------------------------------------------
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/*
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* FLASH related
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*----------------------------------------------------------------------*/
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*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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@ -167,7 +167,8 @@
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#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
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#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_BASE + (12 << 10)) /* Copy SPL here */
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#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
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#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from */
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/* this addr */
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#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
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/*
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@ -202,17 +203,17 @@
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#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
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#endif
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/*-----------------------------------------------------------------------
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/*
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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*/
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#define CFG_MBYTES_SDRAM (256) /* 256MB */
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
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#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
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#endif
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/*-----------------------------------------------------------------------
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/*
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* I2C
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*----------------------------------------------------------------------*/
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*/
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#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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@ -294,8 +295,8 @@
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#define CONFIG_HAS_ETH0
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
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#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx */
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/* buffers & descriptors */
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#define CONFIG_NET_MULTI 1
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#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
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#define CONFIG_PHY1_ADDR 1
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@ -322,7 +323,6 @@
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#define CONFIG_DOS_PARTITION
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#define CONFIG_ISO_PARTITION
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/*
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* BOOTP options
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*/
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@ -332,7 +332,6 @@
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_SUBNETMASK
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/*
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* Command line configuration.
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*/
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@ -367,14 +366,14 @@
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#endif
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/* POST support */
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#define CONFIG_POST (CFG_POST_MEMORY | \
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#define CONFIG_POST (CFG_POST_CACHE | \
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CFG_POST_CPU | \
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CFG_POST_UART | \
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CFG_POST_I2C | \
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CFG_POST_CACHE | \
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CFG_POST_FPU_ON | \
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CFG_POST_ETHER | \
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CFG_POST_SPR)
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CFG_POST_FPU_ON | \
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CFG_POST_I2C | \
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CFG_POST_MEMORY | \
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CFG_POST_SPR | \
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CFG_POST_UART)
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#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
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#define CONFIG_LOGBUFFER
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@ -384,9 +383,9 @@
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#define CONFIG_SUPPORT_VFAT
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/*-----------------------------------------------------------------------
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/*
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* Miscellaneous configurable options
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*----------------------------------------------------------------------*/
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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@ -394,7 +393,8 @@
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
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/* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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@ -412,16 +412,16 @@
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#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
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#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
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/*-----------------------------------------------------------------------
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/*
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* PCI stuff
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*----------------------------------------------------------------------*/
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*/
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CFG_PCI_CACHE_LINE_SIZE 0 /* to avoid problems with PNP */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to */
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/* CFG_PCI_MEMBASE */
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#define CFG_PCI_MASTER_INIT
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@ -430,15 +430,15 @@
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#define CFG_PCI_SUBSYS_ID 0xcafe /* Whatever */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
|
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* For booting Linux, the board info and command line data have to be in the
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* first 8 MB of memory, since this is the maximum mapped by the Linux kernel
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* during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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/*
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
|
||||
/*
|
||||
* On Sequoia CS0 and CS3 are switched when configuring for NAND booting
|
||||
@ -469,15 +469,15 @@
|
||||
|
||||
#define CFG_BCSR5_PCI66EN 0x80
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* NAND FLASH
|
||||
*----------------------------------------------------------------------*/
|
||||
*/
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* PPC440 GPIO Configuration
|
||||
*/
|
||||
/* test-only: take GPIO init from pcs440ep ???? in config file */
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user