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PXA: Cleanup serial_pxa

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* Cleanup register definitions by introducing new regs-uart.h, compliant with
  rest of U-Boot.
* Remove old register definitions from pxa-regs.h
* Convert serial_pxa to new regs-uart.h
* Cleanup serial_pxa

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut 2011-08-28 03:35:13 +02:00 committed by Albert ARIBAUD
parent dd36d806fe
commit 237ce0fe97
3 changed files with 304 additions and 394 deletions
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111
arch/arm/include/asm/arch-pxa/pxa-regs.h
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@ -313,117 +313,6 @@ typedef void (*ExcpHndlr) (void) ;
#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
/******************************************************************************/
/*
* UARTs
*/
/* Full Function UART (FFUART) */
#define FFUART FFRBR
#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
#define FFLCR 0x4010000C /* Line Control Register (read/write) */
#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
#define FFLSR 0x40100014 /* Line Status Register (read only) */
#define FFMSR 0x40100018 /* Modem Status Register (read only) */
#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Bluetooth UART (BTUART) */
#define BTUART BTRBR
#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
#define BTLCR 0x4020000C /* Line Control Register (read/write) */
#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
#define BTLSR 0x40200014 /* Line Status Register (read only) */
#define BTMSR 0x40200018 /* Modem Status Register (read only) */
#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
/* Standard UART (STUART) */
#define STUART STRBR
#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
#define STFCR 0x40700008 /* FIFO Control Register (write only) */
#define STLCR 0x4070000C /* Line Control Register (read/write) */
#define STMCR 0x40700010 /* Modem Control Register (read/write) */
#define STLSR 0x40700014 /* Line Status Register (read only) */
#define STMSR 0x40700018 /* Reserved */
#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
#define IER_DMAE (1 << 7) /* DMA Requests Enable */
#define IER_UUE (1 << 6) /* UART Unit Enable */
#define IER_NRZE (1 << 5) /* NRZ coding Enable */
#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
#define IIR_TOD (1 << 3) /* Time Out Detected */
#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
#define FCR_ITL_1 (0)
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
#define LCR_SB (1 << 6) /* Set Break */
#define LCR_STKYP (1 << 5) /* Sticky Parity */
#define LCR_EPS (1 << 4) /* Even Parity Select */
#define LCR_PEN (1 << 3) /* Parity Enable */
#define LCR_STB (1 << 2) /* Stop Bit */
#define LCR_WLS1 (1 << 1) /* Word Length Select */
#define LCR_WLS0 (1 << 0) /* Word Length Select */
#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
#define LSR_TEMT (1 << 6) /* Transmitter Empty */
#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
#define LSR_BI (1 << 4) /* Break Interrupt */
#define LSR_FE (1 << 3) /* Framing Error */
#define LSR_PE (1 << 2) /* Parity Error */
#define LSR_OE (1 << 1) /* Overrun Error */
#define LSR_DR (1 << 0) /* Data Ready */
#define MCR_LOOP (1 << 4) /* */
#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
#define MCR_RTS (1 << 1) /* Request to Send */
#define MCR_DTR (1 << 0) /* Data Terminal Ready */
#define MSR_DCD (1 << 7) /* Data Carrier Detect */
#define MSR_RI (1 << 6) /* Ring Indicator */
#define MSR_DSR (1 << 5) /* Data Set Ready */
#define MSR_CTS (1 << 4) /* Clear To Send */
#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
/******************************************************************************/ /******************************************************************************/
/* /*
* IrSR (Infrared Selection Register) * IrSR (Infrared Selection Register)

109
arch/arm/include/asm/arch-pxa/regs-uart.h Normal file
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@ -0,0 +1,109 @@
/*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __REGS_UART_H__
#define __REGS_UART_H__
#define FFUART_BASE 0x40100000
#define BTUART_BASE 0x40200000
#define STUART_BASE 0x40700000
#define HWUART_BASE 0x41600000
struct pxa_uart_regs {
union {
uint32_t thr;
uint32_t rbr;
uint32_t dll;
};
union {
uint32_t ier;
uint32_t dlh;
};
union {
uint32_t fcr;
uint32_t iir;
};
uint32_t lcr;
uint32_t mcr;
uint32_t lsr;
uint32_t msr;
uint32_t spr;
uint32_t isr;
};
#define IER_DMAE (1 << 7)
#define IER_UUE (1 << 6)
#define IER_NRZE (1 << 5)
#define IER_RTIOE (1 << 4)
#define IER_MIE (1 << 3)
#define IER_RLSE (1 << 2)
#define IER_TIE (1 << 1)
#define IER_RAVIE (1 << 0)
#define IIR_FIFOES1 (1 << 7)
#define IIR_FIFOES0 (1 << 6)
#define IIR_TOD (1 << 3)
#define IIR_IID2 (1 << 2)
#define IIR_IID1 (1 << 1)
#define IIR_IP (1 << 0)
#define FCR_ITL2 (1 << 7)
#define FCR_ITL1 (1 << 6)
#define FCR_RESETTF (1 << 2)
#define FCR_RESETRF (1 << 1)
#define FCR_TRFIFOE (1 << 0)
#define FCR_ITL_1 0
#define FCR_ITL_8 (FCR_ITL1)
#define FCR_ITL_16 (FCR_ITL2)
#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
#define LCR_DLAB (1 << 7)
#define LCR_SB (1 << 6)
#define LCR_STKYP (1 << 5)
#define LCR_EPS (1 << 4)
#define LCR_PEN (1 << 3)
#define LCR_STB (1 << 2)
#define LCR_WLS1 (1 << 1)
#define LCR_WLS0 (1 << 0)
#define LSR_FIFOE (1 << 7)
#define LSR_TEMT (1 << 6)
#define LSR_TDRQ (1 << 5)
#define LSR_BI (1 << 4)
#define LSR_FE (1 << 3)
#define LSR_PE (1 << 2)
#define LSR_OE (1 << 1)
#define LSR_DR (1 << 0)
#define MCR_LOOP (1 << 4)
#define MCR_OUT2 (1 << 3)
#define MCR_OUT1 (1 << 2)
#define MCR_RTS (1 << 1)
#define MCR_DTR (1 << 0)
#define MSR_DCD (1 << 7)
#define MSR_RI (1 << 6)
#define MSR_DSR (1 << 5)
#define MSR_CTS (1 << 4)
#define MSR_DDCD (1 << 3)
#define MSR_TERI (1 << 2)
#define MSR_DDSR (1 << 1)
#define MSR_DCTS (1 << 0)
#endif /* __REGS_UART_H__ */

466
drivers/serial/serial_pxa.c
View File

@ -1,4 +1,6 @@
/* /*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
*
* (C) Copyright 2002 * (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de> * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
* *
@ -32,148 +34,161 @@
#include <watchdog.h> #include <watchdog.h>
#include <serial.h> #include <serial.h>
#include <asm/arch/pxa-regs.h> #include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h> #include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
#define FFUART_INDEX 0 /*
#define BTUART_INDEX 1 * The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
* easily handle enabling of clock.
*/
#ifdef CONFIG_CPU_MONAHANS
#define UART_CLK_BASE CKENA_21_BTUART
#define UART_CLK_REG CKENA
#define BTUART_INDEX 0
#define FFUART_INDEX 1
#define STUART_INDEX 2 #define STUART_INDEX 2
#elif CONFIG_PXA250
#define UART_CLK_BASE (1 << 4) /* HWUART */
#define UART_CLK_REG CKEN
#define HWUART_INDEX 0
#define STUART_INDEX 1
#define FFUART_INDEX 2
#define BTUART_INDEX 3
#else /* PXA27x */
#define UART_CLK_BASE CKEN5_STUART
#define UART_CLK_REG CKEN
#define STUART_INDEX 0
#define FFUART_INDEX 1
#define BTUART_INDEX 2
#endif
/*
* Only PXA250 has HWUART, to avoid poluting the code with more macros,
* artificially introduce this.
*/
#ifndef CONFIG_PXA250
#define HWUART_INDEX 0xff
#endif
#ifndef CONFIG_SERIAL_MULTI #ifndef CONFIG_SERIAL_MULTI
#if defined (CONFIG_FFUART) #if defined(CONFIG_FFUART)
#define UART_INDEX FFUART_INDEX #define UART_INDEX FFUART_INDEX
#elif defined (CONFIG_BTUART) #elif defined(CONFIG_BTUART)
#define UART_INDEX BTUART_INDEX #define UART_INDEX BTUART_INDEX
#elif defined (CONFIG_STUART) #elif defined(CONFIG_STUART)
#define UART_INDEX STUART_INDEX #define UART_INDEX STUART_INDEX
#elif defined(CONFIG_HWUART)
#define UART_INDEX HWUART_INDEX
#else #else
#error "Bad: you didn't configure serial ..." #error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
#endif #endif
#endif #endif
void pxa_setbrg_dev (unsigned int uart_index) uint32_t pxa_uart_get_baud_divider(void)
{ {
unsigned int quot = 0;
if (gd->baudrate == 1200) if (gd->baudrate == 1200)
quot = 768; return 768;
else if (gd->baudrate == 9600) else if (gd->baudrate == 9600)
quot = 96; return 96;
else if (gd->baudrate == 19200) else if (gd->baudrate == 19200)
quot = 48; return 48;
else if (gd->baudrate == 38400) else if (gd->baudrate == 38400)
quot = 24; return 24;
else if (gd->baudrate == 57600) else if (gd->baudrate == 57600)
quot = 16; return 16;
else if (gd->baudrate == 115200) else if (gd->baudrate == 115200)
quot = 8; return 8;
else else /* Unsupported baudrate */
hang (); return 0;
}
struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
{
switch (uart_index) { switch (uart_index) {
case FFUART_INDEX: case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
#ifdef CONFIG_CPU_MONAHANS case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
writel(readl(CKENA) | CKENA_22_FFUART, CKENA); case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
#else case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
writel(readl(CKEN) | CKEN6_FFUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
writel(0, FFIER); /* Disable for now */
writel(0, FFFCR); /* No fifos enabled */
/* set baud rate */
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
writel(quot & 0xff, FFDLL);
writel(quot >> 8, FFDLH);
writel(LCR_WLS0 | LCR_WLS1, FFLCR);
writel(IER_UUE, FFIER); /* Enable FFUART */
break;
case BTUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
#else
writel(readl(CKEN) | CKEN7_BTUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
writel(0, BTIER);
writel(0, BTFCR);
/* set baud rate */
writel(LCR_DLAB, BTLCR);
writel(quot & 0xff, BTDLL);
writel(quot >> 8, BTDLH);
writel(LCR_WLS0 | LCR_WLS1, BTLCR);
writel(IER_UUE, BTIER); /* Enable BFUART */
break;
case STUART_INDEX:
#ifdef CONFIG_CPU_MONAHANS
writel(readl(CKENA) | CKENA_23_STUART, CKENA);
#else
writel(readl(CKEN) | CKEN5_STUART, CKEN);
#endif /* CONFIG_CPU_MONAHANS */
writel(0, STIER);
writel(0, STFCR);
/* set baud rate */
writel(LCR_DLAB, STLCR);
writel(quot & 0xff, STDLL);
writel(quot >> 8, STDLH);
writel(LCR_WLS0 | LCR_WLS1, STLCR);
writel(IER_UUE, STIER); /* Enable STUART */
break;
default: default:
hang(); return NULL;
} }
} }
void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
clk_reg = UART_CLK_REG;
clk_offset = UART_CLK_BASE << uart_index;
reg = readl(clk_reg);
if (enable)
reg |= clk_offset;
else
reg &= ~clk_offset;
writel(reg, clk_reg);
}
/*
* Enable clock and set baud rate, parity etc.
*/
void pxa_setbrg_dev(uint32_t uart_index)
{
uint32_t divider = 0;
struct pxa_uart_regs *uart_regs;
divider = pxa_uart_get_baud_divider();
if (!divider)
hang();
uart_regs = pxa_uart_index_to_regs(uart_index);
if (!uart_regs)
hang();
pxa_uart_toggle_clock(uart_index, 1);
/* Disable interrupts and FIFOs */
writel(0, &uart_regs->ier);
writel(0, &uart_regs->fcr);
/* Set baud rate */
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
writel(divider & 0xff, &uart_regs->dll);
writel(divider >> 8, &uart_regs->dlh);
writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
/* Enable UART */
writel(IER_UUE, &uart_regs->ier);
}
/* /*
* Initialise the serial port with the given baudrate. The settings * Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits. * are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/ */
int pxa_init_dev (unsigned int uart_index) int pxa_init_dev(unsigned int uart_index)
{ {
pxa_setbrg_dev (uart_index); pxa_setbrg_dev (uart_index);
return 0;
return (0);
} }
/* /*
* Output a single byte to the serial port. * Output a single byte to the serial port.
*/ */
void pxa_putc_dev (unsigned int uart_index,const char c) void pxa_putc_dev(unsigned int uart_index, const char c)
{ {
switch (uart_index) { struct pxa_uart_regs *uart_regs;
case FFUART_INDEX:
/* wait for room in the tx FIFO on FFUART */
while ((readl(FFLSR) & LSR_TEMT) == 0)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
writel(c, FFTHR);
break;
case BTUART_INDEX: uart_regs = pxa_uart_index_to_regs(uart_index);
while ((readl(BTLSR) & LSR_TEMT) == 0) if (!uart_regs)
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ hang();
writel(c, BTTHR);
break;
case STUART_INDEX: while (!(readl(&uart_regs->lsr) & LSR_TEMT))
while ((readl(STLSR) & LSR_TEMT) == 0) WATCHDOG_RESET();
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ writel(c, &uart_regs->thr);
writel(c, STTHR);
break;
}
/* If \n, also do \r */ /* If \n, also do \r */
if (c == '\n') if (c == '\n')
@ -185,17 +200,15 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
* otherwise. When the function is succesfull, the character read is * otherwise. When the function is succesfull, the character read is
* written into its argument c. * written into its argument c.
*/ */
int pxa_tstc_dev (unsigned int uart_index) int pxa_tstc_dev(unsigned int uart_index)
{ {
switch (uart_index) { struct pxa_uart_regs *uart_regs;
case FFUART_INDEX:
return readl(FFLSR) & LSR_DR; uart_regs = pxa_uart_index_to_regs(uart_index);
case BTUART_INDEX: if (!uart_regs)
return readl(BTLSR) & LSR_DR;
case STUART_INDEX:
return readl(STLSR) & LSR_DR;
}
return -1; return -1;
return readl(&uart_regs->lsr) & LSR_DR;
} }
/* /*
@ -203,187 +216,86 @@ int pxa_tstc_dev (unsigned int uart_index)
* otherwise. When the function is succesfull, the character read is * otherwise. When the function is succesfull, the character read is
* written into its argument c. * written into its argument c.
*/ */
int pxa_getc_dev (unsigned int uart_index) int pxa_getc_dev(unsigned int uart_index)
{ {
switch (uart_index) { struct pxa_uart_regs *uart_regs;
case FFUART_INDEX:
while (!(readl(FFLSR) & LSR_DR))
/* Reset HW Watchdog, if needed */
WATCHDOG_RESET();
return (char) readl(FFRBR) & 0xff;
case BTUART_INDEX: uart_regs = pxa_uart_index_to_regs(uart_index);
while (!(readl(BTLSR) & LSR_DR)) if (!uart_regs)
/* Reset HW Watchdog, if needed */
WATCHDOG_RESET();
return (char) readl(BTRBR) & 0xff;
case STUART_INDEX:
while (!(readl(STLSR) & LSR_DR))
/* Reset HW Watchdog, if needed */
WATCHDOG_RESET();
return (char) readl(STRBR) & 0xff;
}
return -1; return -1;
while (!(readl(&uart_regs->lsr) & LSR_DR))
WATCHDOG_RESET();
return readl(&uart_regs->rbr) & 0xff;
} }
void void pxa_puts_dev(unsigned int uart_index, const char *s)
pxa_puts_dev (unsigned int uart_index,const char *s)
{ {
while (*s) { while (*s)
pxa_putc_dev (uart_index,*s++); pxa_putc_dev(uart_index, *s++);
}
} }
#if defined (CONFIG_FFUART) #define pxa_uart(uart, UART) \
static int ffuart_init(void) int uart##_init(void) \
{ { \
return pxa_init_dev(FFUART_INDEX); return pxa_init_dev(UART##_INDEX); \
} } \
\
void uart##_setbrg(void) \
{ \
return pxa_setbrg_dev(UART##_INDEX); \
} \
\
void uart##_putc(const char c) \
{ \
return pxa_putc_dev(UART##_INDEX, c); \
} \
\
void uart##_puts(const char *s) \
{ \
return pxa_puts_dev(UART##_INDEX, s); \
} \
\
int uart##_getc(void) \
{ \
return pxa_getc_dev(UART##_INDEX); \
} \
\
int uart##_tstc(void) \
{ \
return pxa_tstc_dev(UART##_INDEX); \
} \
static void ffuart_setbrg(void) #define pxa_uart_desc(uart) \
{ struct serial_device serial_##uart##_device = \
return pxa_setbrg_dev(FFUART_INDEX); { \
} "serial_"#uart, \
uart##_init, \
NULL, \
uart##_setbrg, \
uart##_getc, \
uart##_tstc, \
uart##_putc, \
uart##_puts, \
};
static void ffuart_putc(const char c) #define pxa_uart_multi(uart, UART) \
{ pxa_uart(uart, UART) \
return pxa_putc_dev(FFUART_INDEX,c); pxa_uart_desc(uart)
}
static void ffuart_puts(const char *s) #if defined(CONFIG_HWUART)
{ pxa_uart_multi(hwuart, HWUART)
return pxa_puts_dev(FFUART_INDEX,s);
}
static int ffuart_getc(void)
{
return pxa_getc_dev(FFUART_INDEX);
}
static int ffuart_tstc(void)
{
return pxa_tstc_dev(FFUART_INDEX);
}
struct serial_device serial_ffuart_device =
{
"serial_ffuart",
ffuart_init,
NULL,
ffuart_setbrg,
ffuart_getc,
ffuart_tstc,
ffuart_putc,
ffuart_puts,
};
#endif #endif
#if defined(CONFIG_STUART)
#if defined (CONFIG_BTUART) pxa_uart_multi(stuart, STUART)
static int btuart_init(void)
{
return pxa_init_dev(BTUART_INDEX);
}
static void btuart_setbrg(void)
{
return pxa_setbrg_dev(BTUART_INDEX);
}
static void btuart_putc(const char c)
{
return pxa_putc_dev(BTUART_INDEX,c);
}
static void btuart_puts(const char *s)
{
return pxa_puts_dev(BTUART_INDEX,s);
}
static int btuart_getc(void)
{
return pxa_getc_dev(BTUART_INDEX);
}
static int btuart_tstc(void)
{
return pxa_tstc_dev(BTUART_INDEX);
}
struct serial_device serial_btuart_device =
{
"serial_btuart",
btuart_init,
NULL,
btuart_setbrg,
btuart_getc,
btuart_tstc,
btuart_putc,
btuart_puts,
};
#endif #endif
#if defined(CONFIG_FFUART)
#if defined (CONFIG_STUART) pxa_uart_multi(ffuart, FFUART)
static int stuart_init(void) #endif
{ #if defined(CONFIG_BTUART)
return pxa_init_dev(STUART_INDEX); pxa_uart_multi(btuart, BTUART)
}
static void stuart_setbrg(void)
{
return pxa_setbrg_dev(STUART_INDEX);
}
static void stuart_putc(const char c)
{
return pxa_putc_dev(STUART_INDEX,c);
}
static void stuart_puts(const char *s)
{
return pxa_puts_dev(STUART_INDEX,s);
}
static int stuart_getc(void)
{
return pxa_getc_dev(STUART_INDEX);
}
static int stuart_tstc(void)
{
return pxa_tstc_dev(STUART_INDEX);
}
struct serial_device serial_stuart_device =
{
"serial_stuart",
stuart_init,
NULL,
stuart_setbrg,
stuart_getc,
stuart_tstc,
stuart_putc,
stuart_puts,
};
#endif #endif
#ifndef CONFIG_SERIAL_MULTI #ifndef CONFIG_SERIAL_MULTI
inline int serial_init(void) { pxa_uart(serial, UART)
return (pxa_init_dev(UART_INDEX)); #endif
}
void serial_setbrg(void) {
pxa_setbrg_dev(UART_INDEX);
}
int serial_getc(void) {
return(pxa_getc_dev(UART_INDEX));
}
int serial_tstc(void) {
return(pxa_tstc_dev(UART_INDEX));
}
void serial_putc(const char c) {
pxa_putc_dev(UART_INDEX,c);
}
void serial_puts(const char *s) {
pxa_puts_dev(UART_INDEX,s);
}
#endif /* CONFIG_SERIAL_MULTI */