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Merge branch 'next' of git://www.denx.de/git/u-boot-ppc4xx into next

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This commit is contained in:
Wolfgang Denk 2010-12-17 20:10:49 +01:00
commit 2ad6eee1a4
15 changed files with 142 additions and 604 deletions
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28
arch/powerpc/cpu/ppc4xx/start.S
View File

@ -48,21 +48,23 @@
*------------------------------------------------------------------------------- *-------------------------------------------------------------------------------
*/ */
/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards /*
* Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
* *
* The following description only applies to the NOR flash style booting.
* NAND booting is different. For more details about NAND booting on 4xx
* take a look at doc/README.nand-boot-ppc440.
* *
* The processor starts at 0xfffffffc and the code is executed * The CPU starts at address 0xfffffffc (last word in the address space).
* from flash/rom. * The U-Boot image therefore has to be located in the "upper" area of the
* in memory, but as long we don't jump around before relocating. * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
* board_init lies at a quite high address and when the cpu has * the boot chip-select (CS0) is quite big and covers this area. On the
* jumped there, everything is ok. * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
* This works because the cpu gives the FLASH (CS0) the whole * reconfigure this CS0 (and other chip-selects as well when configured
* address space at startup, and board_init lies as a echo of * this way) in the boot process to the "correct" values matching the
* the flash somewhere up there in the memorymap. * board layout.
*
* board_init will change CS0 to be positioned at the correct
* address and (s)dram will be positioned at address 0
*/ */
#include <asm-offsets.h> #include <asm-offsets.h>
#include <config.h> #include <config.h>
#include <asm/ppc4xx.h> #include <asm/ppc4xx.h>
@ -265,7 +267,7 @@
/* NOTREACHED - board_init_f() does not return */ /* NOTREACHED - board_init_f() does not return */
#endif #endif
#if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
/* /*
* 4xx RAM-booting U-Boot image is started from offset 0 * 4xx RAM-booting U-Boot image is started from offset 0
*/ */

8
arch/powerpc/cpu/ppc4xx/u-boot.lds
View File

@ -23,8 +23,12 @@
#include "config.h" /* CONFIG_BOARDDIR */ #include "config.h" /* CONFIG_BOARDDIR */
#ifndef RESET_VECTOR_ADDRESS #ifndef RESET_VECTOR_ADDRESS
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
#else
#define RESET_VECTOR_ADDRESS 0xfffffffc #define RESET_VECTOR_ADDRESS 0xfffffffc
#endif #endif
#endif
OUTPUT_ARCH(powerpc) OUTPUT_ARCH(powerpc)
@ -100,7 +104,11 @@ SECTIONS
* start.o, since the first shadow TLB only covers 4k * start.o, since the first shadow TLB only covers 4k
* of address space. * of address space.
*/ */
#ifdef CONFIG_INIT_TLB
CONFIG_INIT_TLB (.bootpg)
#else
CONFIG_BOARDDIR/init.o (.bootpg) CONFIG_BOARDDIR/init.o (.bootpg)
#endif
} :text = 0xffff } :text = 0xffff
#endif #endif

22
board/lwmon5/sdram.c
View File

@ -45,10 +45,10 @@
* memory. * memory.
* *
* If at some time this restriction doesn't apply anymore, just define * If at some time this restriction doesn't apply anymore, just define
* CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup * CONFIG_4xx_DCACHE in the board config file and this code should setup
* everything correctly. * everything correctly.
*/ */
#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE #ifdef CONFIG_4xx_DCACHE
#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
#else #else
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
@ -220,18 +220,32 @@ phys_size_t initdram (int board_type)
program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
MY_TLB_WORD2_I_ENABLE); MY_TLB_WORD2_I_ENABLE);
#if defined(CONFIG_DDR_ECC)
#if defined(CONFIG_4xx_DCACHE)
/*
* If ECC is enabled, initialize the parity bits.
*/
program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#else /* CONFIG_4xx_DCACHE */
/* /*
* Setup 2nd TLB with same physical address but different virtual address * Setup 2nd TLB with same physical address but different virtual address
* with cache enabled. This is done for fast ECC generation. * with cache enabled. This is done for fast ECC generation.
*/ */
program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#ifdef CONFIG_DDR_ECC
/* /*
* If ECC is enabled, initialize the parity bits. * If ECC is enabled, initialize the parity bits.
*/ */
program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
#endif
/*
* Now after initialization (auto-calibration and ECC generation)
* remove the TLB entries with caches enabled and program again with
* desired cache functionality
*/
remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20);
#endif /* CONFIG_4xx_DCACHE */
#endif /* CONFIG_DDR_ECC */
/* /*
* Clear possible errors resulting from data-eye-search. * Clear possible errors resulting from data-eye-search.

38
board/t3corp/t3corp.c
View File

@ -23,6 +23,7 @@
#include <libfdt.h> #include <libfdt.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <i2c.h> #include <i2c.h>
#include <mtd/cfi_flash.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/mmu.h> #include <asm/mmu.h>
@ -191,3 +192,40 @@ struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
{ {
return board_scan_options; return board_scan_options;
} }
/*
* Accessor functions replacing the "weak" functions in
* drivers/mtd/cfi_flash.c
*
* The NOR flash devices "behind" the FPGA's (Xilinx DS617)
* can only be read correctly in 16bit mode. We need to emulate
* 8bit and 32bit reads here in the board specific code.
*/
u8 flash_read8(void *addr)
{
u16 val = __raw_readw((void *)((u32)addr & ~1));
if ((u32)addr & 1)
return val;
return val >> 8;
}
u32 flash_read32(void *addr)
{
return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
}
void flash_cmd_reset(flash_info_t *info)
{
/*
* FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
* needs the Spansion type reset commands. The other flash chip
* is located behind a FPGA (Xilinx DS617) and needs the Intel type
* reset command.
*/
if (info->start[0] == CONFIG_SYS_FLASH_BASE)
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
else
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}

4
board/xilinx/ppc405-generic/Makefile
View File

@ -41,7 +41,9 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS) all: $(LIB) $(SOBJS)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $^) $(call cmd_link_o_target, $^)
clean: clean:

131
board/xilinx/ppc405-generic/u-boot-ram.lds
View File

@ -1,131 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

141
board/xilinx/ppc405-generic/u-boot-rom.lds
View File

@ -1,141 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start)
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your configuration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

4
board/xilinx/ppc440-generic/Makefile
View File

@ -43,7 +43,9 @@ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS)) OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS)) SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS) all: $(LIB) $(SOBJS)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $^) $(call cmd_link_o_target, $^)
clean: clean:

132
board/xilinx/ppc440-generic/u-boot-ram.lds
View File

@ -1,132 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

142
board/xilinx/ppc440-generic/u-boot-rom.lds
View File

@ -1,142 +0,0 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
ENTRY(_start_440)
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
arch/powerpc/cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
*(.text)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.eh_frame)
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss (NOLOAD) :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(4);
}
ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and CONFIG_SYS_TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}

20
boards.cfg
View File

@ -675,10 +675,10 @@ yellowstone powerpc ppc4xx yosemite amcc
yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
yucca powerpc ppc4xx - amcc yucca powerpc ppc4xx - amcc
AP1000 powerpc ppc4xx ap1000 amirix AP1000 powerpc ppc4xx ap1000 amirix
fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x03000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xFFCB0000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x03000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xFF1C0000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds v5fx30teval_flash powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
CRAYL1 powerpc ppc4xx L1 cray CRAYL1 powerpc ppc4xx L1 cray
CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1 CATcenter powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1
CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25 CATcenter_25 powerpc ppc4xx PPChameleonEVB dave - CATcenter:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
@ -736,12 +736,12 @@ p3p440 powerpc ppc4xx - prodriv
KAREF powerpc ppc4xx karef sandburst KAREF powerpc ppc4xx karef sandburst
METROBOX powerpc ppc4xx metrobox sandburst METROBOX powerpc ppc4xx metrobox sandburst
xpedite1000 powerpc ppc4xx - xes xpedite1000 powerpc ppc4xx - xes
ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds ml507 powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds ml507_flash powerpc ppc4xx ml507 xilinx - ml507:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc440-generic/init.o
xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-ram.lds xilinx-ppc405-generic powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC
xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc405-generic/u-boot-rom.lds xilinx-ppc405-generic_flash powerpc ppc4xx ppc405-generic xilinx - xilinx-ppc405-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-ram.lds xilinx-ppc440-generic powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x03FFFFFC,BOOT_FROM_XMD=1
xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xFE360000,SYS_LDSCRIPT=$(SRCTREE)/board/xilinx/ppc440-generic/u-boot-rom.lds xilinx-ppc440-generic_flash powerpc ppc4xx ppc440-generic xilinx - xilinx-ppc440-generic:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC
rsk7203 sh sh2 rsk7203 renesas - rsk7203 sh sh2 rsk7203 renesas -
mpr2 sh sh3 mpr2 - - mpr2 sh sh3 mpr2 - -
ms7720se sh sh3 ms7720se - - ms7720se sh sh3 ms7720se - -

22
include/configs/lwmon5.h
View File

@ -43,6 +43,8 @@
#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */ #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */ #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
@ -321,6 +323,8 @@
/* Update size in "reg" property of NOR FLASH device tree nodes */ /* Update size in "reg" property of NOR FLASH device tree nodes */
#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
#define CONFIG_FIT /* enable FIT image support */
#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */ #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
#define CONFIG_PREBOOT "setenv bootdelay 15" #define CONFIG_PREBOOT "setenv bootdelay 15"
@ -393,16 +397,18 @@
#define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN
/* USB */ /*
#ifdef CONFIG_440EPX * USB/EHCI
#define CONFIG_USB_OHCI */
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
#define CONFIG_EHCI_DCACHE /* with dcache handling support */
#define CONFIG_EHCI_MMIO_BIG_ENDIAN
#define CONFIG_EHCI_DESC_BIG_ENDIAN
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
#define CONFIG_USB_STORAGE #define CONFIG_USB_STORAGE
/* Comment this out to enable USB 1.1 device */
#define USB_2_0_DEVICE
#endif /* CONFIG_440EPX */
/* Partitions */ /* Partitions */
#define CONFIG_MAC_PARTITION #define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION #define CONFIG_DOS_PARTITION

18
include/configs/t3corp.h
View File

@ -120,11 +120,16 @@
*/ */
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */ #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ (CONFIG_SYS_FPGA1_BASE + 0x01000000) }
#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
0xbddf } /* set async read mode */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/ #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
@ -355,6 +360,7 @@
"ramdisk_addr=fc200000\0" \ "ramdisk_addr=fc200000\0" \
"pciconfighost=1\0" \ "pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \ "pcie_mode=RP:RP\0" \
"unlock=yes\0" \
"" ""
/* /*
@ -423,7 +429,7 @@
EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \ EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \ EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED) EBC_BXAP_PEN_DISABLED)
@ -440,7 +446,7 @@
EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \ EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \ EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED) EBC_BXAP_PEN_DISABLED)
@ -457,7 +463,7 @@
EBC_BXAP_WBN_ENCODE(0) | \ EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \ EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \ EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \ EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \ EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \ EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED) EBC_BXAP_PEN_DISABLED)

1
include/configs/xilinx-ppc.h
View File

@ -50,6 +50,7 @@
#undef CONFIG_CMD_DHCP #undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_EEPROM #undef CONFIG_CMD_EEPROM
#undef CONFIG_CMD_IMLS #undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NFS
/*Misc*/ /*Misc*/
#define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */ #define CONFIG_BOOTDELAY 5/* autoboot after 5 seconds */

35
post/cpu/ppc4xx/ether.c
View File

@ -34,7 +34,10 @@
* are transmitted. The configurable test parameters are: * are transmitted. The configurable test parameters are:
* MIN_PACKET_LENGTH - minimum size of packet to transmit * MIN_PACKET_LENGTH - minimum size of packet to transmit
* MAX_PACKET_LENGTH - maximum size of packet to transmit * MAX_PACKET_LENGTH - maximum size of packet to transmit
* TEST_NUM - number of tests * CONFIG_SYS_POST_ETH_LOOPS - Number of test loops. Each loop
* is tested with a different frame length. Starting with
* MAX_PACKET_LENGTH and going down to MIN_PACKET_LENGTH.
* Defaults to 10 and can be overriden in the board config header.
*/ */
#include <post.h> #include <post.h>
@ -77,8 +80,12 @@ DECLARE_GLOBAL_DATA_PTR;
#endif #endif
#define MIN_PACKET_LENGTH 64 #define MIN_PACKET_LENGTH 64
#define MAX_PACKET_LENGTH 256 #define MAX_PACKET_LENGTH 1514
#define TEST_NUM 1 #ifndef CONFIG_SYS_POST_ETH_LOOPS
#define CONFIG_SYS_POST_ETH_LOOPS 10
#endif
#define PACKET_INCR ((MAX_PACKET_LENGTH - MIN_PACKET_LENGTH) / \
CONFIG_SYS_POST_ETH_LOOPS)
static volatile mal_desc_t tx __cacheline_aligned; static volatile mal_desc_t tx __cacheline_aligned;
static volatile mal_desc_t rx __cacheline_aligned; static volatile mal_desc_t rx __cacheline_aligned;
@ -361,29 +368,27 @@ static int packet_check (char *packet, int length)
return 0; return 0;
} }
char packet_send[MAX_PACKET_LENGTH];
char packet_recv[MAX_PACKET_LENGTH];
static int test_ctlr (int devnum, int hw_addr) static int test_ctlr (int devnum, int hw_addr)
{ {
int res = -1; int res = -1;
char packet_send[MAX_PACKET_LENGTH];
char packet_recv[MAX_PACKET_LENGTH];
int length; int length;
int i;
int l; int l;
ether_post_init (devnum, hw_addr); ether_post_init (devnum, hw_addr);
for (i = 0; i < TEST_NUM; i++) { for (l = MAX_PACKET_LENGTH; l >= MIN_PACKET_LENGTH;
for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { l -= PACKET_INCR) {
packet_fill (packet_send, l); packet_fill (packet_send, l);
ether_post_send (devnum, hw_addr, packet_send, l); ether_post_send (devnum, hw_addr, packet_send, l);
length = ether_post_recv (devnum, hw_addr, packet_recv, length = ether_post_recv (devnum, hw_addr, packet_recv,
sizeof (packet_recv)); sizeof (packet_recv));
if (length != l || packet_check (packet_recv, length) < 0) { if (length != l || packet_check (packet_recv, length) < 0) {
goto Done; goto Done;
}
} }
} }